Clock mesh has been widely adopted in microprocessor designs to distribute clock signal to clock sink nodes. The primary goal of clock mesh design is to minimize undesired difference in clock arrival time between different sink nodes, which is also known as clock skew. Moreover, the needs for high-performance low-power chip designs impose other constraints on the clock mesh design such as limited power dissipation and area consumption. Due to the enormous size of clock mesh and those complex constraint conditions, achieving an optimal clock mesh design is very challenging. Most of the gradient-based optimization methods require quick yet accurate calculation of gradients/sensitivities information. In this paper, we present a precise yet efficient adjoint sensitivity analysis framework which computes the sensitivity of clock mesh performance metric with respect to every circuit parameter. By evolving the traditional adjoint sensitivity analysis into an application-specific, customized adjoint sensitivity analysis framework, the daunting task of computing clock mesh performance metric sensitivity with respect to hundreds of thousands of circuit parameters can be accomplished very efficiently, making the optimization as well as incremental design approaches for clock mesh tractable.