Wednesday, March 6, 2019
8:45am–9:45am |
Meeting Rooms 203/204
Keynote Speech: |
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8:45am–9:45am | Adversarial attacks on Security and Privacy of Machine Learning Systems Sandip Kundu - National Science Foundation(NSF) |
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9:45am-10:00am |
Morning Break |
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10:00am–11:20am |
Machine Learning in Conventional and Emerging Platforms
Meeting Room 201 |
Modern High-Level and Logic Synthesis
Meeting Room 206 |
Emerging Memory and Spintronics Technologies for Future Energy Efficient Applications Meeting Room 207 |
11:20am–12:00pm |
Sponsored by Synopsys Meeting Rooms 203/204
Best Paper Awards Committee Recognition |
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12:00pm–1:25pm | Luncheon Panel Discussion Hype or hope: Is machine learning the next generation of design and design automation? |
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1:25pm-1:35pm | Break | ||
1:35pm–2:35pm | Embedded Tutorial 1 Tools and approaches to efficiently implement Deep Learning in embedded systems Presenter: Meeting Rooms 203/204 |
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2:35pm-3:35pm | Embedded Tutorial 2 Spiking Neural Networks for Artificial Vision. From Sensing, to Processing and Learning Presenter: Meeting Rooms 203/204 |
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3:35pm-3:45pm | Afternoon Break | ||
3:45pm–5:25pm |
Advances in Simulation, Design Optimization and Debug
Meeting Room 201 |
System Level Tools, Flows, Methods
Meeting Room 206 |
High Performance Application Specific Architecture
Meeting Room 207 |
5:25pm–6:55pm | Poster Papers & Mixer Room: Atrium |
Thursday, March 7, 2019
9:00am–9:45am |
Meeting Rooms 203/204
Keynote Speech: |
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9:00am–9:45am |
Amit Gupta - General Manager of the IC Verification Solutions Solido division of Mentor, a Siemens Business |
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9:45am-10:00am | Morning Break |
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10:00am–11:20am |
Deep Learning Circuits and Architecures
Meeting Room 201 |
Innovations In Classic Hardware Security Problems
Meeting Room 206 |
Co-Optimizations of Device Performance and Design Reliability from State-of-the-art FinFET to Quantum Technologies
Meeting Room 207 |
11:20am–11:40am |
Morning Break |
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11:40am–1:00pm |
Artificial Intelligence for Efficient Application Specific Hardware
Meeting Room 201 |
Verification, ATPG and Failure Analysis
Meeting Room 206 |
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1:00pm-1:30pm |
Lunch Break |
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1:30pm-2:30pm | Embedded Tutorial 3 Developments and Practices for Testing MRAM Memories Presenter: Meeting Rooms 203/204 |
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2:30pm-3:30pm | Embedded Tutorial 4 High Energy Efficient Reconfigurable Neural Network Processor Design Presenter: Meeting Rooms 203/204 |
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3:30pm-3:40pm | Break | ||
3:40pm-5:00pm |
Physical Design Optimization
Meeting Room 201 |
3D Integration & Advanced Packaging Future of SOC Architectures and Verification Meeting Room 206 |
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*This is a preliminary program and is subject to change