Chair & Moderators:
Shiyan Hu - Michigan Technological University (Chair)
José Pineda de Gyvez- Eindhoven University of technology (Chair)
Jie Gu- Northwestern University (Co-Chair)
Wednesday, March 6, 1:35:00PM-2:35PM
Tools and approaches to efficiently implement Deep Learning in embedded systems
Dr. Marc Duranton, CEA (French Atomic Energy Commission)
Abstract: Artificial Intelligence, and more particularly Deep Learning are enablers of new applications, and allow computing systems to better interact with the real world by extracting information from signals, images and sounds. But they are demanding in computing power and therefore energy, and pose challenges for being used in embedded systems. This presentation will present some uses cases, tools, approaches and hardware allowing to select neural networks and hardware implementations tuned for embedded applications (Deep Learning at the edge). It will also include some highlight on Auto-ML and on computations using “spiking” data representation.”
About Marc Duranton
Dr. Marc Duranton is a member of the Architecture, IC Design & Embedded Software Division of the Research and Technology Department of CEA (French Atomic Energy Commission), where he is involved in realizations for Deep Learning and on Cyber Physical Systems. He previously spent more than 23 years in Philips and Philips Semiconductors where he led the development of the family of L-Neuro chips, digital processors using artificial neural networks techniques. He also worked on several video coprocessors for the VLIW processor TriMedia and for various Nexperia platforms. In NXP Semiconductors, he was in charge of Ne-XVP project that targeted the design of the hardware and software of a multi-core processor for real-time applications and for consumer video processing.
His interests include Deep Learning, Artificial Intelligence and emerging paradigms for computing systems, HPC, embedded systems, (Cognitive) Cyber Physical Systems, parallel architectures for high performance and real-time processing, models of computation and communication with time guaranties. He is a member of the College of Ethics of CEA on "Moral issues in automatic decision-making processes".
Wednesday, March 6, 2:35PM-3:35PM
Spiking Neural Networks for Artificial Vision. From Sensing, to Processing and Learning
Dr. B. Linares-Barranco, Scientist , Instituto de Microelectronica de Sevilla
Abstract: The brain processes information in a very efficient manner by using some kind of spike encoding technique, despite the fact that the underlying technology (neurons) is slow, faulty, and noisy. Since decades neuromorphic engineering has attempted to imitate the sensing and processing of biological neural systems with the hope to develop artificial systems capable of approaching the brain capabilities. We will present CMOS spiking vision sensors and spiking based processing techniques that allow for extremely fast recognition capabilities. Additionally, emerging memory technologies (such as RRAM) have the potential to be exploited for implementing self-learning and/or highly compact spike processing systems. We will review show some techniques for implementing such capabilities.
About B. Linares-Barranco
B. Linares-Barranco received a PhD degree in 1990 from Univ. of Sevilla, Spain on Analog CMOS Oscillators, and a second PhD degree from Texas A&M Univ. in 1991 on CMOS Analog Neural Networks Implementations. In 1991 he became Tenured Scientist of the Spanish Research Council (CSIC) at the "Instituto de Microelectronica de Sevilla" (Sevilla Microelectronics Institute). In 2004 he was promoted to CSIC Full Professor, and since February 2018 he is the Director of the Institute. His research has focused on Neuromorphic Engineering, developing event-driven (spiking) vision sensors, convolution processors, and unsupervised spike-based learning systems. He is co-founder of Prophesee and GrAI-Matter-Labs, two companies whose objectives include commercializing spiking vision sensor applications. During the past two decades he has been involved in several European projects for developing spiking systems, neuromorphic computing systems, and application of emerging memory nanotechnologies to neuromorphic systems. He has also been part of the Human Brain Project (European Commission Flagship).
Thursday, March 7, 1:30PM-2:30PM
Developments and Practices for Testing MRAM Memories
Patrick Girard, LIRMM - CNRS / France
Abstract: Memories occupy most of the silicon area in nowadays System-on-Chips. Though widely used, non-volatile Flash memories still have several drawbacks. MRAMs have the potential to mitigate almost all Flash related issues. However, they are prone to defects as any other kind of memories. This embedded tutorial provides an up-to-date and practical coverage of MRAM testing. The first part gives some background on Magnetic Tunnel Junction and existing MRAM technologies. Then, an MRAM architecture used to illustrate the development of test and reliability solutions is presented. The next part detailed resistive-open, resistive-bridge and capacitive defect injection campaigns that are usually performed in order to analyze specific failure mechanisms of MRAMs. Specific functional fault models associated to these failure mechanisms are then described. The last part of the tutorial presents March test algorithms developed for MRAM testing and their validation in industrial environments.
About Patrick Girard
Patrick GIRARD received a M.Sc. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research Director at CNRS (French National Center for Scientific Research) and works in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) - France. From 2010 to 2014, he was head of this Microelectronics Department. He is co-Director of the International Associated Laboratory « LAFISI » (French-Italian Research Laboratory on Hardware-Software Integrated Systems) created in 2013 by the CNRS and the University of Montpellier with the Politecnico di Torino, Italy. His research interests include all aspects of digital testing and memory testing, with emphasis on critical constraints such as timing and power. Reliability and fault tolerance are also part of his research activities. He has served on numerous conference committees and is the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE). He is also an Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on CAD and the Journal of Electronic Testing – Theory and Applications (JETTA - Springer). He has supervised 37 PhD dissertations and has published 7 books or book chapters, 65 journal papers, and more than 230 conference and symposium papers on these fields. Patrick Girard is a Fellow of IEEE.
Thursday, March 7, 2:30PM-3:30PM
High Energy Efficient Reconfigurable Neural Network Processor Design
Dr. Shouyi Yin, Professor/Vice Director , Institute of Microelectronics Tsinghua University
Abstract: With the rapid development of information technology, the emerging applications, especially artificial intelligence (AI), bring severe challenges to both energy efficiency (the ratio of performance to energy consumption) and flexibility of computing chips. The traditional computing chips with software programming (such as CPU) or hardware programming (such as FPGA) are difficult to meet the requirements of high energy efficiency. Application Specific Integrated Circuit (ASIC) has high energy efficiency, but the poor flexibility restricts its application under the pressure of high cost of <10nm process technology. Coarse-grained reconfigurable computing is a promising solution which combines high energy-efficiency of hardwired logics and high flexibility of software programming. In the reconfigurable architecture, computing units, storage units and interconnection resources compose a regular parallel and distributed processing element (PE) array, which is dynamic reconfigurable. The software applications (programmed by high-level language, such as C) are synthesized into configuration context for reconfiguring hardware resources at run time. In this tutorial, a survey of basic ideas and recent techniques of coarse-grained reconfigurable architecture (CGRA) is presented. A preliminary analysis of the current challenges and future trends of AI processors are introduced to understand the system constraints, and translate them into design specifications. Then several practical reconfigurable processors are presented to demonstrate the potential and benefits of CGRA. As particularly important case, low-power neural networks processors are discussed by highlighting the “reconfigurability” that are enabling the recent and very rapid improvements in energy efficiency.
About Dr. Shouyi Yin
Dr. Shouyi Yin received the B.S., M.S., and Ph.D. degrees in electronic engineering from Tsinghua University, Beijing, China, in 2000, 2002, and 2005, respectively. He has worked with Imperial College, London, U.K., as a Research Associate. He is currently associate professor (Tenured) and vice director of Institute of Microelectronics in Tsinghua University. His research interests include reconfigurable computing, domain-specific reconfigurable architecture design and high level synthesis. He has published more than 100 journal papers and more than 50 conference papers. He has received ACM/IEEE ISLPED Design Contest Award (2017), Second Prize of China’s State Technological Innovation Award (2015), China’s Patent Golden Award (2015), First Prize of Technological Innovation Award of Ministry of Education, China (2014), and Best Paper Award in China Communications IC Technology and Application Conference (2011). Dr. Shouyi Yin is the Secretary-General of EDA Chapter in Chinese Institute of Electronics. He is also the technical committee member of Asia Pacific Signal and Information Processing Association. Dr. Shouyi Yin has been served as program committee member and organizer in the tops VLSI and EDA conferences such as A-SSCC, DAC, ICCAD and ASPDAC. He is the associate editor of Integration, the VLSI journal and editorial board member of Journal of Low Power Electronics.