28^th International Symposium on Quality Electronic Design (ISQED'27) Call for Papers

For any question please contact the publication committee by sending email to isqedisqed@gmail.com. Note the following important dates:

IMPORTANT DATES (Midnight, US Pacific Time)
FINAL Paper Submission Deadline	Nov. 17, 2026
Acceptance Notification	Jan. 22. 2027
Camera-Ready Paper Due	Feb 17, 2027
Presentation Video, and Speaker Bio	March 20, 2027

Papers are requested in the following areas

A pioneer and leading multidisciplinary conference, ISQED accepts and promotes papers related to the manufacturing, design and EDA. Authors are invited to submit papers in the various disciplines of high level design, circuit design (digital, analog, mixed-signal, RF), test & verification, design automation tools; processes; flows, device modeling, semiconductor technology, advance packaging, and biomedical & bioelectronic devices. All past Conference proceedings & Papers have been published in IEEE Xplore digital library and indexed by Scopus.

The details of various topics of paper submission are as follows:

Agentic AI, Generative AI, EDA Tools and Methodologies (EDA)

Agentic AI, generative AI, and large language models (LLMs) for electronic design automation, including autonomous design agents, intelligent EDA workflows, and AI-assisted circuit and system design
Machine learning and AI-driven EDA methodologies for design-space exploration, optimization, synthesis, placement, routing, and physical design
EDA tools, design flows, and methodologies for digital, analog, mixed-signal, and RF circuits and systems
AI-assisted design verification, debugging, and design-rule checking, including automated testbench generation and verification workflows
Design automation for analyzing and mitigating process variations, aging effects, soft errors, and reliability challenges
IP design automation, integration, reuse, and qualification, including automated IP validation and interoperability
EDA methodologies for chiplets, 2.5D/3D ICs, heterogeneous integration, and advanced packaging, including multi-die design automation and optimization
Modeling, simulation, and design-technology co-optimization (DTCO), including technology computer-aided design (TCAD) and process-aware design methodologies
EDA tools and methodologies for emerging computing paradigms, including neuromorphic, in-memory, and quantum computing
Design automation for silicon photonics, optical interconnects, and electronic-photonic integrated circuits
EDA tools and methodologies for MEMS, NEMS, and other emerging micro/nano-scale systems
Open-source and interoperable EDA platforms, cloud-based design automation, and emerging methodologies for collaborative and scalable electronic design
Other emerging topics related to electronic design automation tools, platforms, algorithms, and methodologies

Hardware and System Security, Trust, and Assurance (HSS)

Hardware attacks, vulnerabilities, and countermeasures, including side-channel attacks, fault injection, hardware Trojans, reverse engineering, and physical tampering
Hardware security primitives and cryptographic implementations, including physically unclonable functions (PUFs), true random number generators (TRNGs), lightweight cryptography, and secure key management
Secure processor and SoC architectures, including trusted execution environments (TEEs), hardware roots of trust, secure boot, and hardware-enforced isolation
Hardware security for AI/ML systems and accelerators, including protection against adversarial attacks, model extraction, intellectual property theft, and data leakage
Security and trust in semiconductor supply chains, including third-party IP protection, counterfeit detection, chip authentication, and secure fabrication and manufacturing
Security of chiplet-based, heterogeneous, and 3D integrated systems, including die-to-die communication, inter-chip trust, and multi-die attack surfaces
Post-quantum cryptography (PQC) hardware architectures, accelerators, and secure implementations
Security of embedded systems, Internet of Things (IoT), edge devices, and cyber-physical systems, including hardware-based protection and secure firmware
Hardware-assisted system security, including secure memory, confidential computing, information-flow protection, and runtime threat detection
Security verification, vulnerability assessment, and hardware-based intrusion detection, including formal security analysis and security-aware design methodologies
Security and trust challenges in emerging semiconductor devices, memory technologies, and computing platforms
Other emerging topics related to hardware security, trusted computing, and resilient electronic systems

Design Test and Verification (DTV)

Formal, assertion-based, simulation-based, and hybrid verification techniques for hardware and software systems
Design-for-Testability (DFT), Automatic Test Equipment (ATE), and Built-In Self-Test (BIST) for digital, analog/mixed-signal, SoC, and memory components
Test synthesis and synthesis-for-testability for improved coverage and quality
Fault diagnosis, IDDQ testing, novel test methods, fault modeling, ATPG, and DPPM prediction
SoC and IP testing strategies, including hierarchical and system-level test approaches
Design methodologies linking testability to manufacturing and yield improvement
Hardware/software co-verification and co-validation strategies
Advanced verification methodologies and testbenches, including UVM, HDLs, and HVLs
Formal and semi-formal validation techniques supporting functional safety and security
Self-checking testbenches and novel methods for analog/mixed-signal verification
Any other emerging topics related to design test and verification

Emerging Semiconductor Devices, Technologies & Processes (EDPT)

Advanced transistor architectures and nanoscale semiconductor technologies, including gate-all-around (GAA) FETs, nanosheet/nanowire transistors, complementary FETs (CFETs), and emerging device scaling techniques
Beyond-CMOS devices and emerging materials, including 2D semiconductors, ferroelectric devices, negative-capacitance FETs, and novel switching technologies for next-generation logic and memory
Design, simulation, and modeling of emerging solid-state devices and materials
Emerging non-volatile memory and logic technologies, such as STT-RAM, PC-RAM, RRAM, and memristors
Applications of emerging devices in advanced computing domains, including cognitive, neuromorphic, and quantum computing
Qubit technologies and quantum circuits for quantum information processing
Specialty device technologies, including MEMS, NEMS, and other nanoelectronic devices
Design-Technology Co-Optimization (DTCO) methodologies across ASIC, FPGA, RF, memory, and custom/semi-custom designs
Advanced-node manufacturing techniques, including EUV lithography, directed self-assembly (DSA), and multiple patterning
Advanced interconnect solutions, including air-gap structures and silicon photonics
Modeling and optimization of emerging technology impacts on power, performance, area, cost, and reliability
Design methods and tools for improving yield, manufacturability, and process robustness
Other topics relevant to emerging device, process, and integration technologies

Circuit Design, Chiplets, 3D Integration & Advanced Packaging (ICAP)

Chiplet architectures and heterogeneous integration, including partitioning, interoperability, modular design, and system-level optimization
2.5D/3D IC integration and advanced packaging, including silicon interposers, bridges, through-silicon vias (TSVs), hybrid bonding, and wafer-level packaging
Die-to-die and chip-to-chip interconnects, including UCIe, high-bandwidth interfaces, signaling, and communication architectures
3D IC and chiplet design methodologies, including EDA flows, floorplanning, placement, routing, and multi-die design optimization
Chip-package-system co-design, including signal integrity, power integrity, thermal management, and mechanical reliability
Testing, verification, and reliability of chiplet-based and 3D systems, including design-for-testability (DFT), known-good-die strategies, yield optimization, and fault tolerance
Silicon photonics and co-packaged optics (CPO), including photonic-electronic integration, optical interconnects, heterogeneous packaging, and chiplet-based optical I/O architectures
Advanced digital, analog, RF, and mixed-signal circuit design, including low-power, high-performance, and variation-tolerant circuits
Emerging circuit architectures for AI and high-performance computing, including compute-in-memory, near-memory computing, and energy-efficient accelerators
Advanced memory and interconnect circuits, including high-bandwidth memory interfaces, emerging memory technologies, and on-chip/inter-die communication
Power management and energy-efficient circuit techniques, including leakage reduction, dynamic power optimization, and power delivery for multi-die systems
Adaptive, resilient, and self-monitoring circuits, including process-voltage-temperature (PVT) monitoring, aging compensation, and fault-tolerant design
Circuits for IoT, edge AI, and emerging applications, including wireless interfaces, sensors, energy harvesting, and ultra-low-power systems
Emerging device and circuit technologies, including beyond-CMOS circuits, novel integration approaches, and new design paradigms
Other topics related to circuit design, chiplets, 3D integration, heterogeneous integration, and advanced packaging

Advanced Systems, Architectures & Design Methodologies (SDM)

Architecture and design methodologies for complex computing systems, including multi-core and many-core processors, SoCs, GPUs, embedded systems, accelerators, and heterogeneous computing platforms
Processor and microarchitecture design and optimization, including domain-specific and workload-optimized architectures
Hardware/software co-design and co-optimization, including compiler–architecture interaction and cross-layer optimization
System-level design-space exploration and multi-objective optimization for performance, power, energy, area, cost, reliability, and other design objectives
System-level power, energy, and thermal management, including dynamic and workload-aware optimization techniques
Memory-system architectures and optimization, including memory hierarchies, caches, shared memory systems, high-bandwidth memory, and memory-centric architectures
System communication and interconnect architectures, including Networks-on-Chip (NoCs), coherent interconnects, memory fabrics, and scalable communication architectures
Application- and workload-driven system architecture, including systems for data centers, edge computing, automotive, IoT, scientific computing, and other domain-specific applications
Modeling, simulation, and performance analysis of computing systems, including architectural and system-level modeling frameworks
Analysis and mitigation of process, voltage, temperature, aging, and workload variations at the architecture and system levels
Reliability, resilience, fault tolerance, and adaptive system architectures
Cyber-Physical Systems (CPS) architecture, modeling, design methodologies, and reliability
FPGA-based and reconfigurable computing systems, including system prototyping, emulation, and hardware/software platforms
Virtual platforms, digital twins, and system-level models for architecture exploration, performance evaluation, and hardware/software development
Cross-layer optimization methodologies spanning applications, software, operating systems, compilers, architecture, and hardware
System-level integration and architectural evaluation of emerging computing and memory technologies, where the primary contribution is at the system or architecture level
Benchmarking, workload characterization, and evaluation methodologies for computing architectures and complex systems
Other emerging topics related to computer architecture, system-level design, modeling, hardware/software co-design, and system optimization

Cognitive Computing Hardware (CCH)

Neuromorphic computing, non-Von Neumann architectures, and brain-inspired hardware paradigms
Hardware and architectures for neural networks, including deep learning and spiking neural networks
Neural network acceleration using GPGPUs, FPGAs, dedicated ASICs, and custom silicon
Cognitive-inspired computing systems and fundamentals for intelligent information processing
AI-assisted cognitive computing methods and hardware/software co-design approaches
Hardware architectures and techniques for reliable and robust machine learning, including fault tolerance, error resilience, and dependable AI acceleration
Cognitive computing in large-scale systems: big data processing, sensing, and interaction
Brain analysis and neuroscience-driven models for hardware design
Internet of Cognitive Things, cognitive environments, and data-driven sensing systems
Cognitive robots, intelligent agents, and edge intelligence platforms
Energy-efficient and scalable cognitive computing hardware, including low-power neural processing, adaptive architectures, and resource-constrained AI systems
Testbeds, prototype implementations, and emerging applications of cognitive hardware
Other topics related to cognitive and intelligent computing hardware

Submission of Papers

Paper submissions must be made online through the ISQED 2027 paper submission portal at https://softconf.com/p/isqed2027/. Authors are invited to submit original, previously unpublished papers accompanied by an abstract of approximately 200 words. Manuscripts must be a minimum of four (4) pages and must not exceed ten (10) pages. A font size of at least 10 points must be used, and manuscripts must conform to the IEEE conference paper format available at https://www.ieee.org/conferences/publishing/templates. Manuscripts exceeding ten (10) pages, using a font size smaller than 10 points, or not conforming to the required IEEE format will not be reviewed. Submissions of fewer than four (4) pages will be considered Work-in-Progress (WIP) papers and reviewed accordingly. To ensure a blind review process, authors must not include their names, affiliations, or any other identifying information in the manuscript or abstract. Complete contact information for the corresponding author must be entered separately through the online submission system.
The manuscripts identifying the name and/or affiliations of the authors in the submitted manuscript will be rejected without review. Please check the as-printed appearance of your paper before sending your paper. In case of any problems email isqedisqed@gmail.com.

See the MS Word template at the bottom of this page. Use the on-line paper submission procedure by clicking the following link: ON-LINE. If you have problem accessing the paper submission site it is located at: https://softconf.com/p/isqed2027

Work in Progress (WIP) Submission

Ongoing research projects can be presented at ISQED under the Work in Progress (WIP) category. This provides a unique opportunity to authors to receive early feedback on their current work. For more information please click HERE.

Workshop/Tutorial Proposals

Several workshop/tutorial sessions will be held on the first day, and would offer valuable opportunities for practicing professionals to refresh or upgrade their skills in quality-based IC design techniques, methodologies and tools. These sessions are intended to supplement the conference by providing in depth, practical and proven design solutions. Workshops/Tutorials will be taught by experts in the field, who are intimately involved with the issues and solutions in their perspective areas, from both industry and academia. If interested in offering a tutorial, please send your tutorial proposals to the ISQED workshop/tutorial committee to isqedisqed@gmail.com

The proposal should include:

Title of Workshop/Tutorial
Name of organizer
Name(s), address, and affiliation of the Moderator
Name(s), address, and affiliation of presenter(s)
Half-page summary of each presenter's biography

You may send your proposal by email as text or as an Adobe PDF file. The presentations must be technical, up to date, relevant, and target the design community. Marketing presentations will not be accepted. In order to meet the conference timeline, we would like to have your proposal no later than Oct. 22, 2026. Please check the archive section of the web site for a listing of past tutorials.

Templates and Resouces for Authors & Speakers

ISQED

28th International Symposium on Quality Electronic Design (ISQED'27) Call for Papers

IMPORTANT DATES (Midnight, US Pacific Time)