ISQED 2009 CONFERENCE AT A GLANCE

Date

Time

TUTORIALS

Room: Monterey/Carmel

Design Technologies and Opportunities for Nano-Scale Era:

Monday 3/16/09

9:00am-5:00pm

Tuesday 3/17/09

8:30am-10:15am

PLENARY SESSION 1P

(Room: Fir/oak)

Keynote Speeches by:

Chi Foon Chan – Synopsys

Rajeev Madhavan – Magma Design Automation

Simon Bloch – Mentor Graphics

10:15am-10:30am

Morning Break

10:30am-12:00pm

Session 1A

Aging Aware Design

Room: Monterey

Session 1B

Robust Circuits

Room: Carmel

Session 1C

Library & Modeling

Room: Santa Clara

Session 1D

Design & Modeling in Emerging Technologies

Room: San Jose

12:00pm-1:30pm

ISQED LUNCHEON

Sponsored by Synopsys

Third Annual ISQED Quality Award (IQ Award 2009)

Sponsored by Mentor

Best Paper Awards

Sponsored by Magma, and Synopsys

Committee Recognition Awards

(Room: Fir/Oak)

Luncheon Keynote

Terry Ma, VP Engineering, Synopsys 

1:30pm-3:00pm

Session 2A
Circuits for Noise & Variation Tolerance

Room: Monterey

Session 2B
Power vs Performance Trade-offs

Room: Carmel

Session 2C
Process Variation

Room: Santa Clara

Embedded

Sessions

2D

Room:

 Donner

EXHIBITS

Room:

 Cascade, Siskiyou

3:00pm-3:30pm

Afternoon Break

3:30pm-5:00pm

Session 3A
System Level Modeling & Design

Room: Monterey

Session 3B
System & Interface Validation

Room: Carmel

Session 3C
Quality Digital Design

Room: Santa Clara

Embedded

Session

3D

Room:

 Donner

5:00pm-6:300pm

6:30pm-8:30pm

Panel Discussion & Dinner

(Room: Fir/oak)

Sponsored by Mentor Graphics

DFM: Insurance Policy or Secret Weapon?

Wednesday 3/18/09

8:30am-10:15am

PLENARY SESSION 2P

(Room: Fir/oak)

Keynote Speeches by:

Peter McGuinness – IMG

Mike Smayling – Tala Innovation

Jim Elliott - Samsung Semiconductor

10:15am-10:30am

Morning Break

10:30am-12:00pm

Session 4A

Co Design Applications for IC Packaging

Room: Monterey

Session 4B

Novel Design Methodologies

Room: Carmel

Session 4C

Memory Design Solutions

Room: Santa Clara

Session 4D

Embedded Tutorial

Functional Verification Planning and Management

Room: San Jose

12:00pm-1:30pm

Lunch Break

1:30pm-3:30pm

Session 5A

Clock and Noise

Room: Monterey

Session 5B

Powe Analysis & Delivery Systems

Room: Carmel

Session 5C

Test Power and Noise

Room: Santa Clara

Session 5D

Embedded Tutorial

Design & Verification of Low Power SoCs

Room: San Jose

3:30pm-3:45pm

 Afternoon Break

3:45pm-5:45pm

Session 6A

Advances in Timing Analysis & Floor Planning

Room: Monterey

Session 6B

Low Voltage Design

Room: Carmel

Session 6C

Low Voltage & Variation Tolerant Design

Room: Santa Clara

Session 6D

System Power & Reliability

Room: San Jose