Session 4D

ISQED09 Embedded Tutorial

Wednesday March 18, 2009

10:30am-12:00noon

Room: Carmel

Functional Verification Planning and Management

Quantifying the Path From Specification to Fully Functional Design 

Speakers:

Shankar Hemmady

Synopsys

Badri Gopalan

Synopsys

Summary:   Functional verification is the main bottleneck of the hardware design process. Currently 50%–70% of the total design effort is consumed by functional verification. In addition, functional bugs are the main cause of additional tape-outs. The increasing complexity of hardware designs, coupled with time-to-market pressures and the high cost of bug escapes, mean that ad-hoc methods for verification planning and execution are no longer adequate. This tutorial teaches the student state-of-the-art techniques and methodologies that are used in the industry today for planning, monitoring and assessing verification progress. Planning, monitoring and assessment of the verification process are essential for predictable, successful verification. Quantifying the scope of the verification problem, specifying its solution and measuring verification progress against this plan dramatically reduces schedule uncertainty and provides an adaptive framework for accommodating design and schedule changes. This planning process provides the information necessary to predict the state of the verification process for risk analysis and management. Overall, good planning, monitoring and assessment prevent late schedule and quality surprises. We focus specifically on the quantification process in this 90-minute tutorial. Good planning, monitoring and assessment of the verification process are comprised of many ingredients. They start with a verification plan that captures the features of the design, taking into account complex and high-risk units as well as scheduling and resource constraints. An important aspect of a good verification plan is a description of the means to measure verification progress. These include monitoring many aspects of the verification process, such as coverage, simulation jobs and cycles, failures and bugs. Another important aspect of the verification plan is whether or not it is executable. Are progress metrics visible in the context of the verification plan? Does the verification plan serve as a design-specific verification assessment interface? The verification plan must also specify the verification techniques to be applied to solve the verification problem. Available technologies include simulation, assertion-based verification and formal analysis. We discuss how to choose design features that are candidates for verification using each of these techniques so that the overall verification labor is minimized while verification completeness is maximized. The tutorial should be of interest to people that are working in the field of hardware and software design and functional verification. This includes: logic designers and verification engineers that need to verify complex hardware designs as part of their everyday job, people that are involved in leading and management of verification projects who can learn from successful experience of their peers and researchers and students in academia who may identify issues related to the topic and use it as a trigger for new research work.   Outline: ● Introduction ● Verification Basics ○ Taxonomy and terminology ○ Technologies ● Verification Planning Process ○ Verification plan structure ○ Verification planning methodology ○ Verification scope ○ Verification solution ○ Verification planning automation ○ Verification planning example ● Executable Verification Plan ○ High level flow ○ Detailed data flow ● Summary 2