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ISQED09 TUTORIALS
Monday, March 16, 2009
9:00am 5:00pm
Rooms: Carmel/Monterey
Chair & Moderator:
Rajiv Joshi, IBM T J Watson Research Center, NY
Presenters:
Swarup Bhunia, Case Western Reserve University
Kaushik Roy, Purdue University
Roger Cheek, IBM
Pat Drennan, Solido Design Automation
Syed M. Alam, Everspin Technologies
Jerry Bautista, Intel
Variation-Tolerant Low-Power Logic Circuits
Presenter:
Swarup Bhunia, Case Western Reserve University
Design considerations for low power operation and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-Vth assignment and gate sizing can have large negative impact on parametric yield under process variations. In this tutorial, we focus on circuit/architectural design techniques for logic circuits to achieve low power operation under parameter variations while minimizing design overhead. Statistical design for low power, voltage scaling and supply gating approaches will be presented. The tutorial will cover major post-silicon process adaptation or healing techniques using voltage scaling or clock stretching. Techniques to deal with within-die parameter variations in logic circuits will be discussed with emphasis on frequency assignments and body biasing. We will also address temperature-aware design and dynamic adaptation to temperature induced parameter variations.
Robust SRAMs in sub-45nm Technology
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Presenter:
Kaushik Roy, Purdue University
Parameter variations and leakage are major concerns in SRAM design in sub-45nm technology. In the first part of the talk, we will present process variation induced failures (read, write, access, hold) in 6T cells and introduce various self-tuning and self-healing schemes to improve memory yield in scaled technologies. Other bitcell configurations for improved memory stability with high dynamic range (supply voltage) will also be presented. In the second part of the talk, we will consider double gate technologies such as FinFETs and technology/circuit co-design for SRAMs.
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Presenter:
Roger Cheek, IBM
Phase-change memory is being touted by many as the eventual replacement for Flash memory, and even DRAM and hard drive storage in some applications. This tutorial introduces this new memory technology. Phase-change memory is faster than flash memory, inherently non-volatile, robust, radiation hard, highly scalable, and compatible with current CMOS processing. These memory devices are possible because of some unusual properties found in a class of materials known as the chalcogenides. Namely, they may be switched back and forth between crystalline and amorphous phases very quickly, and these phases have dramatically different electrical properties. In a memory device the chalcogenide phase-change material operates as a variable resistor, with a range of resistivity of at least three orders of magnitude. We will discuss the nature of the rapid phase change, the attendant property changes, and the techniques used to accomplish the phase change in useful memory devices.
Statistical techniques for analog circuits
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Presenter:
Pat Drennan, Solido Design Automation
Designing integrated circuits about variation is not just about getting global process corners to meet specification (i.e. fast-fast, slow-slow, etc). Global process corners do not accurately represent manufacturing. They do not include local variation and they are built for digital circuit objectives. We use them because there isn’t anything better. Excess margin is added to the design, but how much power and area is wasted? Better statistical tools are needed to balance over-design against under-design. This paper will discuss how to combine the accuracy of Monte Carlo simulation with the speed of corners into an efficient flow using “true corners”. True corners are specific to your circuit, are built around local and global variation and include environmental variables. This approach preserves traditional design flow. True corners based at higher sigma (e.g. 4-sigma) account for design margin in a non-arbitrary way. At even larger-sigma levels (e.g. 6-sigma) they can be used to design many replicated circuits as in the case of memories.
New Design Considerations and Computer-Aided Design Opportunities in Emerging 3D Integration Technology
Presenter:
Syed M. Alam, Everspin Technologies
With continued advancements in process technology, three-dimensional (3D) integration using die or wafer level bonding is emerging as a promising solution for high interconnect bandwidth, differentiated technology integration, and smaller form factor in complex System-on-a-Chip (SoC) design. Following a brief introduction to various types of 3D integration technology, we will discuss multiple system design trade-offs that need to be carefully considered for choosing 3D integration over other integration schemes, such as SiP and SoC. The first step towards enabling 3D design is characterizing the new vertical connection elements, microconnects and through-Si vias (TSVs), in a bonded 3D technology. Electrical modeling and characterization of microconnects and TSVs will be presented along with their delay and power consumption trends over various technology generations. Multiple cost-effective design (e.g. 3D die reuse, design-for-test) considerations and techniques for 3D interface circuitry design will be discussed. Adding the third dimension to design opens up new opportunities for EDA tools and design/architectural techniques to fully explore new approaches and address the challenges of 3D integration. Need for specific EDA tools and new analysis capabilities will be highlighted.
Presenter:
Jerry Bautista, Intel
Many core CPU's are increasingly becoming the norm for client, server, and high performance computing systems. This direction is driven by a need to continue the roughly 2 x performance every two years that the compute industry has delivered for the last decades. The traditional path of performance increases through faster clocking is proving more difficult given ever more stringent power limits at the platform level as well as leakage at the transistor level with decreasing process critical dimensions. We will explore some of the critical design parameters (area vs power tradeoffs) for many core systems as well as challenges at the platform level to provide sufficient I/O, particularly memory bandwidth, to feed the execution of ever demanding highly parallel applications. In addition, we will touch on some of the programming challenges for efficient task dispatch and coordinated execution flow.