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Description:
The external
specifications of an IC (functionality, clock rate, power consumption,
etc.) determine the competitiveness of a product. To be successful and
profitable in the IC business, designers need to “out-design” their
competitors. Although Design-For-Manufacturing (DFM) has typically been
viewed as a yield improvement strategy, mastering DFM can also provide a
competitive advantage in terms of design optimization. The premise is
simple: if designers can selectively reduce the size of guard bands
based on superior knowledge of how physical design features interact
with manufacturing variability, they can design a product with more
competitive performance specifications. In effect, DFM provides the
sensitivity analysis needed to “tighten up” the design process. This can
be done not only for one design, but based on cumulative process data
from all designs at a given technology node. DFM then becomes an
integral part of the classical yield learning process.
This panel will explore
how DFM can give designers a competitive “lever” by informing
them—through manufacturing process simulations calibrated to real
silicon data—how far they can push a design without risking a yield
disaster.
Items to be discussed
and debated include:
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Rules vs.
modeling…is it just a matter of preference?
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Can RDRs and
pre-tuned IP alone deliver competitive advantage?
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Different
approaches to physical signoff and their relation to business
goals
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Advancing
signoff from functional yield to parametric yield
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DFM as an
engineering discipline
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Who should be
driving DFM, fabs or FPGA IP supplier
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Panelists:
Walter Ng
Vice President
Design Enablement Alliances
Chartered Semiconductor
Manufacturing Inc.
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Walter Ng
is responsible for customer and partner alliances for
adoption of Chartered Semiconductor’s 45nm solutions, and
setting strategy for 32nm. Previously, Ng served as senior
director of design solutions managing Chartered's
relationships with third-party EDA and IP partners. He holds
a B.S.E.E. and M.B.A. degrees from the University of
Massachusetts. |
Juan C. Rey
Senior Engineering Director
Design to Silicon Division
Mentor Graphics Corporation
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Juan C. Rey
is the Senior Engineering Director for the Design to Silicon
Division at Mentor Graphics Corporation. His group is
responsible for the architecture, design and development of
the Calibre line of products used for integrated circuits
physical verification and tape out tasks such as design rule
checking, layout vs. schematic verification, capacitance,
resistance and inductance extraction, resolution
enhancement, mask data preparation and design for
manufacturing. Juan has 25 years of software development
experience ranging from research activities at Stanford
University (EE department), to development and management
(at Technology Modeling Associates, Cadence and Mentor
Graphics) of electronics design automation and process and
device modeling software. |
Luigi Capodieci, Ph.D.
R&D Fellow
AMD/The Foundry Co.
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Dr. Luigi
Capodieci has been working on lithographic imaging and
process simulations for 15 years, with applications to
Optical Proximity Correction, Phase Shift Masks, and
Resolution Enhancement Technology. At Advanced Micro
Devices, in California, he pioneered the field of Design For
Manufacturability (DFM), integrating physical design CAD
flows with rigorous layout printability process modeling and
novel verification algorithms. He is currently a Fellow at
AMD/The Foundry Company, coordinating advanced RET/OPC and
DFM R&D from 45 and 32nm, down to the next generations of 22
and 15nm technology nodes. Dr. Capodieci holds a Doctor
degree in Electronic Engineering and Computer Science from
the University of Bologna, Italy, and a Ph.D. in Electrical
Engineering, from the University of Wisconsin-Madison, where
he worked at the Center for Nanotechnology (CNTech, formerly
Center for X-Ray Lithography). |
Yervant Zorian, Ph.D.
Vice President and Chief
Scientist
Virage Logic Corp.
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Yervant
Zorian is the Vice President and Chief Scientist of Virage
Logic Corp. Previously, he was a Distinguished Member of
Technical Staff at AT&T Bell Laboratories, Princeton, New
Jersey. He is currently the President of the IEEE Test
Technology Technical Council, and serves as the
Editor-in-Chief Emeritus of the Journal on Design & Test of
Computers. He received an MS degree in Computer Engineering
from USC, a PhD in Electrical Engineering from McGill
University, and an MBA from Wharton School of Business,
University of Pennsylvania. Dr. Zorian has authored more
than 300 scientific papers, four books, holds 20 US patents,
and received numerous best scientific paper awards. A Fellow
of the IEEE, he was selected by Electronic Engineering Times
among the top 13 influencers on the semiconductor industry
in the past fifty years. Dr. Zorian was the 2005 recipient
of the prestigious Industrial Pioneer Award, and the 2006
recipient of the IEEE Hans Karlsson Award. |
Steve Schumann
Vice President of Corporate Engineering
Atmel Corporation
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Steve
Schumann has served as Atmel’s Vice President of
Corporate Engineering since July of 2007. In this role
he leads development teams responsible for digital
libraries, design methodology, embedded volatile and
nonvolatile memories, and core IP blocks. Previously,
Mr. Schumann was Vice President of Atmel’s non-volatile
memories and has worked on the development of Atmel
memories since starting with the company in 1985. Mr.
Schumann holds a Bachelor of Science degree from the
University of California at Berkeley. |
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