International Symposium on Quality Electronic Design (ISQED)

ISQED 2024 Panel Discussion


Wednesday, April 3, 2024

AI Hardware: Opportunities and Challenges

Chair & Moderator
Ahmedullah Aziz - University of Tennessee Knoxville (Chair)


Arnab Raha - Intel
Garrett S. Rose - University of Tennessee Knoxville
Akhilesh Jaiswal - University of Wisconsin Madison

Summary: In the contemporary fabric of our civilization, artificial intelligence (AI) has emerged as a pivotal force, permeating various facets of our daily lives. Its significance lies in its ability to augment human capabilities, streamline processes, and catalyze breakthroughs in fields ranging from healthcare to finance. As AI applications become increasingly sophisticated, the importance of dedicated hardware tailored to meet the unique computational demands of these intelligent systems has come to the forefront. The growing complexity of AI algorithms, particularly in the realm of deep learning, necessitates specialized hardware architectures. Such dedicated AI hardware serves as the backbone for processing vast amounts of data and executing intricate calculations with remarkable speed and efficiency. This optimized hardware not only accelerates the training and inference processes but also contributes to the scalability and practicality of AI applications. As AI continues to evolve, researchers are uncovering novel algorithms and models that push the boundaries of what is achievable. In this dynamic landscape, the hardware supporting AI must adapt and innovate to fully realize the potential of emerging technologies. The symbiotic relationship between AI advancements and specialized hardware underscores the critical role that hardware research plays in shaping the trajectory of artificial intelligence, ensuring its seamless integration into the fabric of our technologically driven civilization. Embark on a riveting exploration of AI hardware with our expert panel. Explore the expansive potential of advanced processors and innovative accelerators, dissecting the intricate landscape that defines artificial intelligence hardware. Seasoned experts guide the audience through the dual lens of opportunities and challenges, addressing key facets such as scalability, energy efficiency, and the symbiotic interplay with software. This panel promises a compelling journey into the forefront of AI hardware, where challenges are viewed as gateways to innovation, shaping the future of computational prowess. Join us for a captivating exploration of the evolving landscape at the intersection of hardware technology and artificial intelligence.


Arnab Raha Arnab Raha

About Arnab Raha

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Akhilesh Jaiswal Akhilesh Jaiswal

About Akhilesh Jaiswal

Dr. Akhilesh Jaiswal is an Assistant Professor of Electrical and Computer Engineering at the University of Wisconsin-Madison. His wider research interests include application driven device-circuit-system co-design using existing and alternate state variables for intelligent computing platforms. More specifically, Dr. Jaiswal's current research interests include enabling AI at extreme-edge using processing-in-pixel and processing-in-sensor technology, in-memory-computing, hardware-software co-design for efficient distributed computing, bio-inspired paradigms for sensing and compute including neuromorphic systems, electro-optic general-purpose computing among others. He has authored several articles in leading peer-reviewed journals and conferences and has 27 issued patents with and several pending patents.





Garrett S. Rose Garrett S. Rose

About Garrett S. Rose

Garrett S. Rose (Senior Member, IEEE) received the B.S. degree in computer engineering from Virginia Polytechnic Institute and State University, Blacksburg, VA, USA, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of Virginia, Charlottesville, VA, USA, in 2003 and 2006, respectively. His Ph.D. dissertation was on the topic of circuit design methodologies for molecular electronic circuits and computing architectures. From May 2004 to August 2005, he was with MITRE Corporation, McLean, VA, USA, where he was involved in the design and simulation of nanoscale circuits and systems. From August 2006 to May 2011, he was an Assistant Professor with the Department of Electrical and Computer Engineering, Polytechnic Institute of New York University, Brooklyn, NY, USA. From June 2011 to July 2014, he was with the Air Force Research Laboratory, Information Directorate, Rome, NY, USA. He is currently a Professor and Associate Department Head with the Min H. Kao Department of Electrical Engineering and Computer Science, The University of Tennessee Knoxville, TN, USA, where his work is focused on research in the areas of nanoelectronic circuit design, neuromorphic computing, and hardware security. His current research interests include low-power circuits, system-on-chip design, trusted hardware, and developing VLSI design methodologies for novel nanoelectronic technologies.


Ahmedullah Aziz Ahmedullah Aziz

About Ahmedullah Aziz

Ahmedullah Aziz is an Assistant Professor of Electrical Engineering & Computer Science at the University of Tennessee, Knoxville, USA. He earned his Ph.D. in ECE from Purdue University in 2019, an MS degree in EE from the Pennsylvania State University (University Park) in 2016, and a BS degree in EE from Bangladesh University of Engineering & Technology (BUET) in 2013. Before beginning his graduate studies, Dr. Aziz worked in the 'Tizen Lab' of the Samsung R&D Institute as a full-time Engineer. While at graduate school, he worked as a Co-Op Engineer (Intern) in the Technology Research division of Global Foundries (Fab 8, NY, USA). He received several awards and accolades for his research, including ‘Chancellor’s Innovation Award’ from UT Knoxville, 'ACM SIGDA Outstanding Ph.D. Dissertation Award (2021)' from the Association of Computing Machinery, 'EDAA Outstanding Ph.D. Dissertation Award (2020)' from the European Design and Automation Association, and 'Outstanding Graduate Student Research Award (2019)' from the College of Engineering, Purdue University. He is a technical program committee (TPC) member for multiple flagship conferences and a reviewer for several journals from reputed publishers (IEEE, AIP, Elsevier, Frontiers, IOP Science, Springer Nature). He also served as a review panelist for the US DoE, and NSF. He serves as an editorial board member for multiple journals including - 'Scientific Reports', and 'Frontiers in Neuroscience'. His research portfolio comprises multiple avenues of exploratory nanoelectronics, spanning from device modeling to circuit/array design.