ISQED Best Papers
ISQED Best papers as well as all other ISQED papers are available from IEEE Xplore.
ISQED 2018 |
Jialing Li, Kangjun Bai, Lingjia Liu, Yang Yi Parallel implementation of finite state machines for reducing the latency of stochastic computing Cong Ma and David J. Lilja |
ISQED 2017 |
Re-addressing SRAM Design and Measurement for Sub-Threshold Operation in View of Classic 6T vs. Standard Cell Based Implementations Xin Fan(1), Jan Stuijt(1), Rui Wang(1,2), Bo Liu(1), and Tobias Gemmeke(1,3) Performance-Thermal Trade-offs for a VFI-Enabled 3D NoC Architecture Dongjin Lee, Sourav Das, Partha Pratim Pande |
ISQED 2016 |
Reliability and Energy-aware Cache Reconfiguration for Embedded Systems Yuanwen Huang and Prabhat Mishra Digital IP Protection Using Threshold Voltage Control Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma Vrudhula |
ISQED 2015 |
SChieh-Yang Chen, Wen-Tsung Huang, and Yiming Li A Low-Power Field-Programmable Analog Array for Wireless Sensing Brandon Rumberg and David W. Graham |
ISQED 2014 |
| Runtime 3-D Stacked Cache Data Management for Energy Minimization of 3-D Chip-Multiprocessors Seunghan Lee(1)
, Kyungsu Kang(2)
, Jongpil Jung(1)
, Chong-Min Kyung(1) Statistical Methodology for Modeling Non-IID Memory Fails Events Sabine Francis(1)
, Rouwaida Kanj(1)
, Rajiv Joshi(2)
,
Ayman Kayssi(1)
, Ali Chehab(1) |
ISQED 2013 |
| Peak Power Reduction of a Sensor Network Processor Fabricated With Deeply Depleted Channel Transistors in 65nm Technology Kentaro Kawakami, Takeshi Shiro, Hironobu Yamasaki, Katsuhiro Yoda, Hiroaki Fujimoto,
Kenichi Kawasaki, Yasuhiro Watanabe Cost-effective 45nm 6T-SRAM Reducing 50mV Vmin and 53% Standby Leakage with multi-Vt Asymmetric Halo MOS and Write Assist Circuitry Koji Nii(1), Makoto Yabuuchi(1), Hidehiro Fujiwara(1), Yasumasa Tsukamoto(1), Yuichiro Ishii(1),
Tetsuya Matsumura(1), Yoshio Matsuda(2) LMgr: A Low-Memory Global Router with Dynamic Topology Update and Bending-Aware Optimum Path Search Jingwei Lu(1) and Chiu-Wing Sham(2) |
ISQED 2012 |
| A Self-Testable SiGe LNA and Built-in-Self-Test Methodology for Multiple Performance Specifications of RF Amplifiers Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee,
Duane Howard, and John D. Cressler Device- and System-Level Performance Modeling for Graphene P-N Junction Logic Chenyun Pan and Azad Naeemi |
ISQED 2011 |
| A Design Time Simulator for Computer Architects Sangeetha Sudhakrishnan, Francisco J. Mesa Martinez, Jose Renau Design and Analysis of Metastable-Hardened and Soft- Error Tolerant High-Performance, Low-Power Flip-Flops David Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev Complementary Nano-Electro-Mechanical Switch for Ultra-Low-Power Applications: Design and Modeling Khawla Alzoubi(1), Daniel G. Saab(2), Massood Tabib-Azar(3), Sijing Han(2) |
ISQED 2010 |
| Robust Gate Sizing by Uncertainty Second Order Cone Jin Sun, Janet Wang Scalable Methods for the Analysis and Optimization Jianxin Fang, Sachin S. Sapatnekar |
UC-PHOTON: A Novel Hybrid Photonic network-on-Chip Shirish Bahirat, Sudeep Pasricha |
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ISQED 2009 |
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Small Embeddable NBTI Sensors (SENS) for Tracking On-Chip Performance Decay Adam Cabe, Zhenyu Qi, Stuart Wooters, Travis Blalock, Mircea Stan University of Virginia |
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Power & Variability Test Chip Architecture and 45nm-Generation Silicon-Based Analysis for Robust, Power-Aware SoC Design Ramnath Venkatraman, Ruggero Castagnetti, Andres Teene, Benjamin Mbouombouo, Shiva Ramesh LSI Corporation |
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3D-GCP: An Analytical Model for the Impact of Process Variations on the Critical Path Delay Distribution of 3D ICs Siddharth Garg and Diana Marculescu Carnegie Mellon University |
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ISQED 2008 |
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A methodology for characterization of large macro cells and IP blocks considering process variations |
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Characterization of Standard Cells for
Intra-Cell Mismatch Variations |
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Design Margin Exploration of Spin-Torque
Transfer RAM (SPRAM) |
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ISQED 2007 |
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Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications Amit Laknaur, Rui Xiao, Sai Raghuram Durbha, Haibo Wang Southern Illinois University, Carbondale |
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Arthur Nieuwoudt and Yehia Massoud Rice University |
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A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances Andrew B. Kahng and Rasit O. Topaloglu University of California San Diego |
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ISQED 2006 |
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Improving Transient Error Tolerance of Digital VLSI
Circuits Using
Robustness Compiler (ROCO)
Chong Zhao, Sujit Dey
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System-Level SRAM Yield Enhancement
Fadi Kurdahi *, Ahmed Eltawil
*, Rouwaida Kanj **,
*UC Irvine,
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Power Gating with Multiple Sleep Modes
Kanak Agarwal*, Harmander
Deogun**, Dennis Sylvester**, Kevin Nowka*
*IBM Research,
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FASER: Fast Analysis of Soft Error Susceptibility for
Cell-Based Designs
Bin Zhang, Wei-shen
Wang, Michael Orshansky
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ISQED 2005 |
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Noise Library Characterization for Large Capacity Static Noise Analysis Tools Alex Gyure, Alireza Kasnavi, Sam Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zedja Synopsys Inc., Mountain View, CA |
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A Mask Reuse Methodology for Reducing System-on-a-Chip Cost Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin IBM Corp., Yorktown Heights, NY |
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A New Method for Robust Design of Digital Circuits Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen Boyd Stanford University, Stanford, CA |
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A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing Xin Wang, Charles Chiang, Jamil Kawa, Qing Su Synopsys Inc., Mountain View, CA |
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ISQED 2004 |
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SRAM
Leakage Suppression by Minimizing Standby Supply Voltage |
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Scan BIST Targeting Transition Faults Using a Markov
Source |
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Application Specific Worst Case Corners using Response
Surfaces and Statistical Models |
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Robustness Enhancement through Chip-Package Co-Design for
High-Speed Electronics |
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ISQED 2003 |
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Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay Takashi Sato*, Hiroo Masuda** *Hitachi, Ltd., Kyoto University,Tokyo, Japan, **Semiconductor Technology Academic Research Center, Kanagawa, Japan |
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ISQED 2002 |
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Extending the Viability of ΙDDQ Testing ίη Deep Submicron Era Υ. Tsiatouhas, Integrated Systems Development S.A., Athens, Greece Th. Haniotakis, Southem Illinois University, Carbondale, IL D. Nikolos, University of Patras, Patras, Greece Α. Arapoyanni, University of Athens, Athens, Greece Honorable Mention goes to the following papers: Pre-route Noise estimation in Deep Submicron Integrated Circuits Murat Becer, Motorola, Inc., Austin, ΤΧ David Blaauw, University of Michigan, Αnn Arbor, ΜΙ Rajendran Panda, Motorola, Inc., Austin, ΤΧ Ibrahim Ν. Hajj, University of Illinois, Urbana, IL
Measurement of lnherent Noise in EDA Tools Andrew Β. Kahng, University of Califomia at San Diego, La Jolla, CA Stefanus Mantik, University of Califomia, Los Angeles, CA |
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ISQED 2001 |
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Color Counting and its Application to Path Delay Fault Coverage Jayant Deodhar*, Spyros Tragoudas** *Intel, **Southern Illinois University |
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A System for Automatic Recording and Prediction of Design Quality Metrics Andrew B. Khang, Stefanus Mantik UCLA |
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ISQED 2000 |
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On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques Zhanping Chen*, Liqiong Wei*,Kaushik Roy** *Intel, Purdue University |
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Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells Tomas Bautista and Antonio Nunez University of Las Palmas de Gran Canaria |
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Quick On-Chip Self- and Mutual-Inductance Screen Shen Lin, Norman Chang, Sam Nakagawa Hewlett-Packard Laboratories |