International Symposium on Quality Electronic Design (ISQED)
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Program at a Glance


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Press Room


Keynotes at ISQED 2013

Tuesday & Wednesday March 5-6

The Changing Device Technology

Chenmin Hu Chenming Hu
TSMC Distinguished Professor in Graduate School
University of California, Berkeley

Chenming Hu, TSMC Distinguished Professor of Graduate School, University of California, Berkeley

IC device technology has entered a new era of bold changes. FinFET may be the best known new technology. Ultra-thin-body is an attractive new technology. Even bolder changes are envisioned and needed to empower the semiconductor industry.

About Chenming Hu

Chenming Hu is the TSMC Distinguished Professor of UC Berkeley. He was formerly the Chief Technology Officer of TSMC. He is known for developing the 3D transistor, FinFET, that can be scaled beyond 10nm. He also developed the international-standard MOSFET model used by most IC companies since 1997. He has received the IEEE Andrew Grove Award, Solid State Circuits Award, Nishizawa Medal, and UC Berkeley's highest honor for teaching--the Berkeley Distinguished Teaching Award.




Sustaining Innovation for Smarter Computing in Data Centers

Brad L Brech Brad L Brech
Member of the IBM Academy of Technology

Brad L Brech, Member of the IBM Academy of Technology - IBM

Better business economics and accelerated business velocity are the two most important factors to the CxO's of clients moving forward. They see technology as a key to their success in meeting both goals in this fast moving world. Smarter Computing is about successfully overcoming the challenges of new analytics, cloud, big data and security requirements through use of appropriate technologies. In the end, doing things Smarter and Faster are the driving factors for the Next Generation of Data Centers.

About Brad L Brech

Brad Brech is a Distinguished Engineer in the Systems and Technology Division of IBM in the office of the CTO. He is currently leader of the Systems and Technology Architecture board, where his responsibilities include technical strategy, energy efficient computing, intellectual property development and technical vitality for IBM STG. Brad joined IBM in 1982. He has made many contributions to the mid-range systems from the System/36, AS/400, and Power Systems families in roles from logic design, Chief Firmware architect, and Chief Systems SW Architect. As one of the drivers behind IBM's Project Big Green in 2006, he focused on development and delivery of technologies that help customers increase the level of energy efficiency in their data centers. Brad is an IBM Distinguished Engineer, a member of the IBM Academy of Technology, and a board member of The Green Grid. He has many IBM awards, serves on leadership team for the IBM Academy of Technology, and other corporate technical vitality teams. He has published several papers and reports, holds several patents. He is an alumnus Stevens Institute of Technology. Outside of work he spends time with his family and working on the boards of 3 charitable organizations.

System Level Perspective on Semiconductors for Intelligent Networks

Bill Swift, Vice President of Engineering - Cisco Systems

Bill Swift Bill Swift
Vice President of Engineering
Cisco Systems

The impact of the internet on our lives is accelerating and the innovation required to build the technologies and products for these networks is accelerating with it. Innovations at the semiconductor level, board level, and system level in support of new requirements on signaling, packaging, operation, quality, and reliability are taking analytical, simulation, and compute technologies to new limits. In this keynote, Cisco VP of Engineering Bill Swift highlights technology and business trends, as well as innovation drivers for semiconductor technology in the industry and at Cisco enabling products and solutions for intelligent networks.

About Bill Swift

Bill Swift is the Vice President of Engineering for the Silicon Engineering team in the Cisco Systems Engineering organization. He is currently responsible for silicon development engineering for the service provider, enterprise, and high end switching based products. Bill joined Cisco in 1994 and has held a number of hardware, software and system engineering leadership positions across multiple technologies, developments and platforms including the highly successful 7500, 12K, MGX, CRS, and ASR9K platforms. Prior to that, Bill has led the initial development and integration of many key service provider technologies into Cisco routing products such as packet over sonet, channelized interfaces, IP over optical, and IP over DWDM. Before joining Cisco, Bill worked in product development teams at Tandem Computers on non-stop computing, GTE Telenet on X.25 packet switching and American Satellite Company on satellite communications systems. Bill holds both Bachelor's and Master's degrees in Electrical Engineering from The Johns Hopkins University at Baltimore, Maryland.

Trends in Analog/ Mixed-Signal Design Tools

Ed Petrus, Director of Custom Architecture, DSM division - Mentor Graphics

Ed Petrus Ed Petrus
Director of Custom Architecture, DSM division
Mentor Graphics

Designers who are creating analog/mixed-signal intensive designs are faced with a complex set of challenges. They need to have a high degree of confidence that their designs will be manufacturable and perform to specification in the foundry process before they even consider completing a design in an advanced process node. These ICs are often assembled using multiple resources and various design methodologies including IP reuse, top-down design, and bottom-up design. In the keynote, Ed Petrus discusses the unique challenges of designing custom ICs targeted for smaller manufacturing geometries, and talks about the tools being successfully deployed today while giving insights into what is on the horizon in terms of new functionality.

About Ed Petrus

Ed Petrus is the Director of Custom Architecture for the Deep Submicron division of Mentor Graphics. Before coming to Mentor, Ed was the co-founder of Ciranova where he helped build breakthrough products for automating custom IC physical design. These products are in deployment with design teams at top semiconductor companies using sub-40nm processes. Previous to Ciranova, Ed spent 10 years at Cadence Design Systems where he was an architect and developer of SKILL and other components of Cadence's DFII technology. Before Cadence, Ed started his career in EDA as a software engineer at Daisy Systems. Ed has held engineering management positions at Military Advantage and Nanomix. Ed holds B.Sc. and M.Sc. degrees in Computer Science from the University of Essex in the United Kingdom.

Physical-Aware, High-Capacity RTL Synthesis for Advanced Nanometer Designs

Sanjiv Taneja , Vice President, Product Engineering - Cadence Design Systems

Sanjiv Taneja Sanjiv Taneja
Vice President, Product Engineering
Cadence Design Systems

The small world of sub-20nm is already upon us and has brought a new set of challenges for RTL designers as the race for best PPA (performance, power, and area) continues unabated. Challenges include giga-scale integration of new functionality, new physics effects, new device structures such as FinFETs, interconnect stacks with vastly varying resistance characteristics from bottom to top layers in a non-linear fashion and process variation. These challenges are raising several questions. Can RTL synthesis handle giga-scale, giga-hertz designs in a timeframe of market relevance? Can logic synthesis perform accurate and predictive modeling of the interconnect stack, vias and other physical effects in RTL? How do new device structures affect dynamic and leakage power tradeoff and library choices? How do logic structuring, cell selection, clock gating, and DFT choices change to anticipate and handle routing congestion? And how do we ensure strong correlation between logic synthesis and P&R/signoff? This talk will explore these challenges and provide an overview of state-of-the-art technology to address them in a predictive and convergent design flow.

About Sanjiv Taneja

Sanjiv Taneja is VP of Product Engineering for the Front End Design Group at Cadence Design Systems. Prior to assuming this role in 2010, he led Cadence's Encounter Test R&D group for over five years. He joined Cadence from Bell Laboratories where he led the development of transistor-sizing based technology for low power design. Sanjiv holds a BS degree in EE from IIT New Delhi, MS in Computer Science from Ohio State University and MBA from NYU.

The Lifecycle Of Audio Products, consumer versus professional

Perry Goldstein , Director of Sales & Marketing - Marshall Electronics

Perry Goldstein Perry Goldstein
Director of Sales & Marketing
Marshall Electronics

Most electronics will last many years if they are used in their intended manner. Professional electronics are not necessarily built to last longer, but to perform better. When they are built to meet the needs of the professional user, they will be in use for many more years than if a consumer product is used in a professional environment. This keynote provides a review of electronics lifecycle process, and the elements that make up the process, from a sales and marketing perspective. It will compare the design and lifecycle of consumer and professional electronics. The talk will further explore case studies of actual product applications.

About Perry Goldstein

Perry Goldstein is a veteran of the electronics industry. He spent his career in consumer electronics including 23 years at Panasonic. He is currently Director of Sales & Marketing for Marshall Electronics, manufacturer of broadcast monitors, and MXL recording microphones. He is also a professional speaker and writer for the digital signage industry.