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ISQED'25 Embedded Tutorials

 

Chair & Moderators:
Zhen Zhou - Intel Corporation(Chair)

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Tutorial 1
 Wednesday, April 23, 12:25PM-1:25PM

Scalable and Reliable On-Package I/O: UCIe Innovations and Best Practices

Presenter:
Zuguo (Joe) Wu, Intel

Abstract: Lorem ipsum dolor sit amet, consectetur adipiscing elit. Phasellus ac mattis justo, ut iaculis magna. In maximus interdum ultricies. Quisque lorem dui, ornare non lacinia quis, vehicula tempor nibh. Proin sagittis maximus egestas. Suspendisse convallis ac sapien ut sodales. Curabitur vestibulum ullamcorper turpis, vel facilisis urna molestie non. Sed convallis dictum euismod. Sed porttitor pretium tempus. Pellentesque scelerisque gravida nisi semper sollicitudin. Duis malesuada lectus lobortis rutrum consectetur. Nam ut mauris imperdiet, bibendum risus ut, mattis felis. Sed rutrum mauris ac tortor egestas ultricies. Integer sem augue, dictum tincidunt pharetra nec, aliquam eget quam. Ut a enim at ex placerat euismod. Maecenas ut faucibus ante. Sed turpis quam, blandit ac vulputate at, suscipit vel ante. Sed turpis tortor, vestibulum non augue quis, varius laoreet tellus. Orci varius natoque penatibus et magnis dis parturient montes, nascetur ridiculus mus. Fusce mollis libero at mauris rhoncus tincidunt. Suspendisse vulputate dictum mauris, sit amet pretium velit tincidunt quis. Suspendisse sollicitudin mauris sed dolor efficitur scelerisque. Lorem ipsum dolor sit amet, consectetur adipiscing elit. Integer vitae volutpat tortor.

 

About Zuguo (Joe) Wu
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Quisque bibendum ultrices vestibulum. Phasellus metus ex, faucibus eu bibendum sit amet, tincidunt at mi. Integer tempor lobortis elit, ut vestibulum augue rutrum in. Proin luctus risus eu accumsan vestibulum. Maecenas in purus mauris. In rhoncus eros quis turpis auctor maximus. Vestibulum ante ipsum primis in faucibus orci luctus et ultrices posuere cubilia curae; Sed et felis id nulla dignissim commodo. Curabitur leo tellus, pretium sed nunc ac, imperdiet interdum lacus. Aenean in vehicula arcu. Vivamus aliquam vel ex sit amet aliquet. Fusce non massa vitae nisl dapibus ullamcorper. Quisque vitae tincidunt ante. Cras a enim ipsum. Praesent id eros quis lorem pretium aliquet. Nullam vel tortor ac augue mollis elementum.

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Tutorial 2
 Thuesday, April 24, 1:05PM-2:05PM

TBA

Presenter:
Tolga Acikalin, Lightmatter

Tolga Acikalin

Abstract: Lorem ipsum dolor sit amet, consectetur adipiscing elit. Praesent lobortis semper imperdiet. Integer varius consequat maximus. Morbi non lorem nec lacus venenatis volutpat ac eu sapien. Mauris cursus lectus a sollicitudin volutpat. Proin sem libero, pellentesque quis ante et, lobortis tristique augue. Sed auctor, orci vel consectetur congue, risus enim commodo felis, eu dapibus nunc mi id massa. In imperdiet nisl ut facilisis condimentum. Proin lacinia ex vitae velit venenatis, et convallis turpis viverra. Ut auctor ullamcorper nisl non euismod. Nam suscipit mi at lacus varius, eu aliquam lectus tempus. Phasellus in porta ipsum. Sed efficitur eleifend felis, ut consequat orci tempor maximus. Maecenas a diam eget erat accumsan pellentesque et sed ligula. Aliquam viverra tellus et urna volutpat sagittis. Nulla imperdiet justo sed neque facilisis, aliquet elementum dui faucibus. Quisque faucibus, est non faucibus finibus, risus quam tempor lectus, non pretium quam magna sed risus. Vivamus in ligula eros. Ut sollicitudin tellus nec mauris viverra molestie. Etiam id mattis odio. Phasellus sodales nulla ligula, vel ultrices odio molestie ut. Orci varius natoque penatibus et magnis dis parturient montes, nascetur ridiculus mus. Donec aliquet, turpis ut ornare dictum, diam lectus bibendum ex, et facilisis lacus nisl et metus.

 

About Tolga Acikalin
Tolga Acikalin earned his Bachelor of Science degree in Mechanical Engineering from Middle East Technical University, Ankara, Turkey, and his Master of Science. and Ph.D. degrees from Purdue University, West Lafayette, IN. Joining Intel in 2007 as a Research and Development Engineer, he worked on various assembly and test pathfinding projects in the Technology and Manufacturing Group, Chandler, AZ. Since 2013, he has been at Intel Labs in Santa Clara, CA. He is currently a Principal Engineer with Intel Labs, driving innovative strategies for heterogeneous system integration from package to wafer scale with an emphasis on next generation interconnect technologies. His research focuses on glass for heterogenous integration, co-packaged optics and silicon photonics, optical and sub-THz to THz RF high-speed interconnects, and their respective package architectures. Tolga has authored or co-authored more than 15 peer-reviewed conference and journal papers in leading APS, ASME, and IEEE publications and holds 5 issued patents along with over 30 filed patents.

 

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