ISQED'25 Embedded Tutorials
Chair & Moderators:
Zhen Zhou - Intel Corporation(Chair)
Tutorial 1
Wednesday, April 23, 12:25PM-1:25PM
Scalable and Reliable On-Package I/O: UCIe Innovations and Best Practices
Presenter:
Dr. Zuguo (Joe) Wu, Intel
Zuguo (Joe) Wu Abstract: The transition from traditional System On Chip (SOC) designs to chiplet-based architectures marks a significant evolution in semiconductor technology. This presentation will explore the Universal Chiplet Interconnect Express (UCIe), an open standard that ensures seamless chiplet interoperability within a package. We will delve into the critical innovations of UCIe, highlighting its electrical characteristics, 2D/2.5D/3D packaging, and energy-efficient design that collectively achieve a tenfold reduction in power consumption compared to conventional off-package I/O. A key focus will be on the reliability of densely packed UCIe links, examining the considerations of consistent and error-free data transmission, even at elevated data rates.
About
Zuguo (Joe) Wu
Zuoguo Wu is a Senior Principal Engineer at Intel, where he manages an I/O circuits and architecture team working on the latest interfaces. He currently serves as the UCIe Consortium Electrical Working Group Co-Chair. He is a principal author of the UCIe spec and defined its PHY architecture and circuit and link analysis. He is also a key contributor to every generation of the PCIe spec since 3.0. He holds 147 patents worldwide and has published over 50 external and Intel-internal papers. He earned a PhD in electrical engineering from Texas A&M University.
Tutorial 2
Thuesday, April 24, 1:05PM-2:05PM
Optical Transceivers Enabling High Performance Hardware Infrastructure for AI applications
Presenter:
Dr. Juthika Basak , AMD
Juthika Basak Abstract: In recent years, Large Language Models (LLMs) have played a significant role in advancing Generative Artificial Intelligence (Gen AI). The amount of compute needed (in petaFLOPs) to support such LLMs has grown at an exorbitant rate of approximately 750x every 2 years. However, interconnect, DRAM, and hardware bandwidth have not progressed at the same rate, prompting the semiconductor industry to explore disruptive technologies. Optical interconnects, which have become widespread in long haul and metro haul network applications, offer a promising solution. The need for cost-efficient solutions has also hastened adoption of silicon photonics transceivers, in turn driving design and manufacturing innovations in this domain. Silicon Photonics Integrated Circuits (PICs) also lends itself well to the advanced packaging schemes, such as hybrid bonding to the associated analog circuits, viz. drivers and Transimpedance Amplifiers (TIAs). This results in signal integrity interconnects in compact form-factors. This tutorial delves into the fundamentals of optical transceivers, exploring the challenges and opportunities associated with incorporating optics into AI-centric hardware infrastructure.
About Juthika Basak
Juthika Basak is a Fellow at Advanced Micro Devices (AMD) working on cutting edge of Photonics Technologies for improving interconnect bandwidth and increasing compute capacities. Prior to AMD, Juthika worked at Nokia, architecting and leading its new generation of CSTAR (Coherent Silicon Transmitter and Receiver) Trademark product line. She also managed the Advanced Packaging technology development team, delivering multiple generations of coherent products for long haul networks.
Juthika also worked at Finisar (acquired by II-VI Corporation and further renamed as Coherent), designing pluggable transceivers for long haul interconnect applications. Leading up to her work on transceiver design, she spent several years at Intel Corporation and Infinera Corporation, working on silicon and III-V photonics technologies, respectively. She completed her B. Tech. in Engineering Physics from the Indian Institute of Technology, Bombay and her M.S. and Ph.D. in Electrical Engineering from University of California, Los Angeles.