ISQED'25 Embedded Tutorials
Chair & Moderators:
Zhen Zhou - Intel Corporation(Chair)
Tutorial 1
Wednesday, April 23, 12:25PM-1:25PM
Scalable and Reliable On-Package I/O: UCIe Innovations and Best Practices
Presenter:
Zuguo (Joe) Wu, Intel
Zuguo (Joe) Wu Abstract: The transition from traditional System On Chip (SOC) designs to chiplet-based architectures marks a significant evolution in semiconductor technology. This presentation will explore the Universal Chiplet Interconnect Express (UCIe), an open standard that ensures seamless chiplet interoperability within a package. We will delve into the critical innovations of UCIe, highlighting its electrical characteristics, 2D/2.5D/3D packaging, and energy-efficient design that collectively achieve a tenfold reduction in power consumption compared to conventional off-package I/O. A key focus will be on the reliability of densely packed UCIe links, examining the considerations of consistent and error-free data transmission, even at elevated data rates.
About
Zuguo (Joe) Wu
Zuoguo Wu is a Senior Principal Engineer at Intel, where he manages an I/O circuits and architecture team working on the latest interfaces. He currently serves as the UCIe Consortium Electrical Working Group Co-Chair. He is a principal author of the UCIe spec and defined its PHY architecture and circuit and link analysis. He is also a key contributor to every generation of the PCIe spec since 3.0. He holds 147 patents worldwide and has published over 50 external and Intel-internal papers. He earned a PhD in electrical engineering from Texas A&M University.
Tutorial 2
Thuesday, April 24, 1:05PM-2:05PM
TBA
Presenter:
Tolga Acikalin, Lightmatter
Tolga Acikalin Abstract: Lorem ipsum dolor sit amet, consectetur adipiscing elit. Praesent lobortis semper imperdiet. Integer varius consequat maximus. Morbi non lorem nec lacus venenatis volutpat ac eu sapien. Mauris cursus lectus a sollicitudin volutpat. Proin sem libero, pellentesque quis ante et, lobortis tristique augue. Sed auctor, orci vel consectetur congue, risus enim commodo felis, eu dapibus nunc mi id massa. In imperdiet nisl ut facilisis condimentum. Proin lacinia ex vitae velit venenatis, et convallis turpis viverra. Ut auctor ullamcorper nisl non euismod. Nam suscipit mi at lacus varius, eu aliquam lectus tempus. Phasellus in porta ipsum. Sed efficitur eleifend felis, ut consequat orci tempor maximus. Maecenas a diam eget erat accumsan pellentesque et sed ligula. Aliquam viverra tellus et urna volutpat sagittis. Nulla imperdiet justo sed neque facilisis, aliquet elementum dui faucibus. Quisque faucibus, est non faucibus finibus, risus quam tempor lectus, non pretium quam magna sed risus. Vivamus in ligula eros. Ut sollicitudin tellus nec mauris viverra molestie. Etiam id mattis odio. Phasellus sodales nulla ligula, vel ultrices odio molestie ut. Orci varius natoque penatibus et magnis dis parturient montes, nascetur ridiculus mus. Donec aliquet, turpis ut ornare dictum, diam lectus bibendum ex, et facilisis lacus nisl et metus.
About Tolga Acikalin
Tolga Acikalin earned his Bachelor of Science degree in Mechanical Engineering from Middle East Technical University, Ankara, Turkey, and his Master of Science. and Ph.D. degrees from Purdue University, West Lafayette, IN. Joining Intel in 2007 as a Research and Development Engineer, he worked on various assembly and test pathfinding projects in the Technology and Manufacturing Group, Chandler, AZ. Since 2013, he has been at Intel Labs in Santa Clara, CA. He is currently a Principal Engineer with Intel Labs, driving innovative strategies for heterogeneous system integration from package to wafer scale with an emphasis on next generation interconnect technologies. His research focuses on glass for heterogenous integration, co-packaged optics and silicon photonics, optical and sub-THz to THz RF high-speed interconnects, and their respective package architectures. Tolga has authored or co-authored more than 15 peer-reviewed conference and journal papers in leading APS, ASME, and IEEE publications and holds 5 issued patents along with over 30 filed patents.