International Symposium on Quality Electronic Design (ISQED)
Call for Papers

Program at a Glance


Press Room
Press Room


ISQED'24 Embedded Tutorials


Chair & Moderators:
Zhen Zhou - Intel Corporation(Chair)
Hechen Wang - Intel Corporation(Co-Chair)

Tutorial 2
 Thursday, April 4, 12:25PM-1:25PM

Securing Ubiquitous Devices with Lightweight Circuit Primitives

Prof. Kaiyuan Yang, Rice University

Kaiyuan Yang Kaiyuan Yang

Abstract:Security and privacy are critical challenges to overcome for ubiquitous electronics, including IoT and wearable/implantable devices. Securing these systems faces not only new challenges at system and network levels due to a vast variance of applications, system constructions, and attack surfaces, but also severe hardware resource constraints on computation resources, power consumption, and device cost. To tackle these challenges, significant research efforts have been pursuing specialized hardware-enabled security primitives that could help build a reliable, trustful, and energy-efficient foundation for system security. This tutorial will give an overview of the problems and focus on three hardware security challenges that could be dealt with through novel circuit designs, namely entropy generation, countermeasures against side-channel and fault-injection attacks, and lightweight computing for security. I will review state-of-the-art circuit-enabled security primitives, including our recent work towards all-digital, fully synthesizable, and compact circuit techniques that enable agile SoC development and technology portability. Novel circuit principles that cross the boundary of traditional digital and analog designs have led to significant improvements in the performance and overheads of these security primitives.


About Kaiyuan Yang
Kaiyuan Yang is an Associate Professor of Electrical and Computer Engineering at Rice University, USA, where he leads the Secure and Intelligent Micro-Systems (SIMS) lab. He received his B.S. degree in Electronic Engineering from Tsinghua University, China, in 2012, and his Ph.D. degree in Electrical Engineering from the University of Michigan - Ann Arbor, in 2017. His research interests include low-power integrated circuits and system design for secure and intelligent microsystems, bioelectronics, hardware security, and mixed-signal computing. He is a recipient of the NSF CAREER Award, IEEE SSCS Predoctoral Achievement Award, Best Paper Awards at 2022 ACM MobiCom, 2021 IEEE CICC, 2016 IEEE S&P (Oakland), and 2015 IEEE ISCAS, and several best paper award nominations at premier conferences. He has given invited talks at major conferences including ISSCC, IEDM, ICCAD, RFIC, ASSCC, etc. His work was also recognized as the research highlight of Communications of ACM and ACM GetMobile magazines, the cover of Nature Biomedical Engineering, and Top Picks in Hardware and Embedded Security.

Tutorial 1
 Wednesday, April 3, 12:25PM-1:25PM

Advanced Packaging for Heterogenous Integration

Tolga Acikalin, Intel Labs

Tolga Acikalin Tolga Acikalin

Abstract: Emergence of artificial intelligence and machine learning, specifically recent developments on large language models, along with trends in internet of things and big data is driving new wave of growth in semiconductors. Heterogeneous integration (HI) is a powerful and key enabler to meet the demands of continued growth of computing and communication performance. Heterogeneous integration involves the integration of separately manufactured components with different functions into a higher-level assembly that, in aggregate, provides enhanced functionality and improved operating characteristics. System level co-design and optimization will be key to achieve the best performance where packaging plays a key role. This tutorial will provide a brief evolution of packaging technologies, and focus on advanced packaging architectures for HI. Key features in 2D and 3D interconnects will be presented along with novel packaging materials (e.g. glass) as well as co-packaged optics using silicon photonics. Furthermore in this tutorial, power-delivery and thermal considerations in advanced packaging will be discussed from a system design perspective.


About Tolga Acikalin
Tolga Acikalin earned his Bachelor of Science degree in Mechanical Engineering from Middle East Technical University, Ankara, Turkey, and his Master of Science. and Ph.D. degrees from Purdue University, West Lafayette, IN. Joining Intel in 2007 as a Research and Development Engineer, he worked on various assembly and test pathfinding projects in the Technology and Manufacturing Group, Chandler, AZ. Since 2013, he has been at Intel Labs in Santa Clara, CA. He is currently a Principal Engineer with Intel Labs, driving innovative strategies for heterogeneous system integration from package to wafer scale with an emphasis on next generation interconnect technologies. His research focuses on glass for heterogenous integration, co-packaged optics and silicon photonics, optical and sub-THz to THz RF high-speed interconnects, and their respective package architectures. Tolga has authored or co-authored more than 15 peer-reviewed conference and journal papers in leading APS, ASME, and IEEE publications and holds 5 issued patents along with over 30 filed patents.