ISQED'26 Keynotes
- Check out selected keynotes from previous years.
Wednesday & Thursday, April 8-10
The Next Decade of Chip Design: Agentic AI and Autonomous Silicon Engineering
Houman HomayounDr. Houman Homayoun - Professor - University of California, Davis
Recent advances in large language models have accelerated the adoption of AI in chip design, enabling new forms of assistance for RTL generation, verification, and debugging. However, most existing AI-driven EDA approaches remain limited to prompt-based interaction and isolated task execution, lacking the ability to reason over long design horizons, coordinate across tools, or adapt to complex, evolving design states. As semiconductor systems grow in scale and heterogeneity—and as technology nodes continue to shrink—these limitations increasingly constrain the impact of AI on reducing design time, verification effort, and overall development risk. This talk focuses on the emerging paradigm of agentic AI for chip design, where collections of specialized, interacting agents operate over specifications, RTL, verification environments, and EDA tools to plan, execute, verify, and refine design decisions. We discuss how orchestration of LLMs and domain-specific small language models (SLMs), combined with tool invocation, function calling, retrieval-augmented reasoning, and persistent design memory, is enabling new capabilities in design verification (UVM, formal property generation, regression triage), specification-driven RTL generation, and security-aware design flows. The presentation highlights how agentic frameworks can embed trust, correctness, and security considerations directly into the generation and verification process, enabling early detection of vulnerabilities and systematic reasoning about design intent—pointing toward a future of more autonomous, scalable, and trustworthy chip design workflows.
About Houman Homayoun
Houman Homayoun is currently a Professor in the Department of Electrical and Computer Engineering at the University of California, Davis. He is also the director of the National Science Foundation Center for Hardware and Embedded Systems Security and Trust (CHEST). Before that, he was an Associate Professor in the Department of Electrical and Computer Engineering at George Mason University (GMU). From 2010 to 2012, he spent two years at the University of California, San Diego, as NSF Computing Innovation (CI) Fellow awarded by the CRA-CCC. Houman graduated in 2010 from the University of California, Irvine, with a Ph.D. in Computer Science. He was a recipient of the four-year University of California, Irvine Computer Science Department chair fellowship. Houman received an MS degree in computer engineering in 2005 from the University of Victoria and a BS degree in electrical engineering in 2003 from the Sharif University of Technology. Houman conducts research in hardware security and trust, applied machine learning and AI, data-intensive computing, and heterogeneous computing, where he has published more than 200 technical papers in prestigious conferences and journals on the subject and directed over $10M in research funding from NSF, DARPA, AFRL, NIST, US Congress, and various industrial sponsors. His work received several best paper awards and nominations in various conferences, including GLSVLSI 2016, ICCAD 2019, ICDM 2019, DCAS 2020, ISVLSI 2020, ICCAD 2020, DATE 2022. His CHEST center received congressional support for research in HW security which was included in 2021 National Defense Authorization Act. Houman served as a Member of the Advisory Committee, Cybersecurity Research and Technology Commercialization working group in the Commonwealth of Virginia. He also served as core group member of the hardware security body of knowledge development team supported by the Department of Defense. He was a recipient of the 2010 National Science Foundation computing innovation fellow award by CCC/CRA. Since 2017 he has been serving as an Associate Editor of IEEE Transactions on VLSI. He chaired and co-chaired major conferences in ACM, including Great Lake Symposium on VLSI.
Architecting the Next-generation Compute Platforms with Chiplets using Open Industry Standards
Debendra Das SharmaDr. Debendra Das Sharma - Senior Fellow and Chief I/O Architect, Intel
The next era of computing demands annual exponential performance growth within strict power and cost limits, driven by AI, machine learning, autonomous driving, and IoT applications. Achieving this requires a new paradigm of on-package integration of chiplets for heterogeneous compute, high-bandwidth memory, and advanced communication in an energy-efficient architecture. The chiplet revolution is accelerating this transformation. The chiplet market is projected to exceed $400 billion by 2035 at a 15.7% CAGR (IDTechEx, 2024), and IBS (2023) estimates that over half of all new silicon design starts will use chiplets. At the heart of this movement, the Universal Chiplet Interconnect Express (UCIe) has rapidly emerged as the open standard for seamless, low-power, high-bandwidth on-package communication. A Synopsys (2025) survey shows UCIe in 97% of chiplet designs; over 50% in AI, HPC, and servers, 20% in automotive, and the rest across consumer, storage, and edge devices. With a power efficiency of 0.25 pJ/bit for planar, delivering 1.5 TB/s/mm2, and 0.01 pJ/bit for vertical interconnects, delivering over 100 TB/s/ mm2, UCIe provides orders of magnitude improvement in both power efficiency and bandwidth density over external interconnects like PCI-Express and Ethernet. This keynote explores how UCIe is shaping the next generation of secure, manageable, and scalable systems, driving innovation from cloud to edge, and laying the foundation for a sustainable, intelligent, and interconnected future.
About Debendra Das Sharma
Dr. Debendra Das Sharma is an Intel Senior Fellow at Intel Corporation, responsible for I/O Technologies and Standards. He has been driving PCI-Express, CXL, and UCIe standards across the industry since their inception. He holds more than 220 US patents and 500 patents world-wide. He has been awarded the Distinguished Alumnus Award from IIT, Kharagpur, the 2021 IEEE Region 6 Outstanding Engineer Award, the first PCI-SIG Lifetime Contribution Award, the 2022 IEEE Circuits and Systems Industrial Pioneer Award, and the 2024 IEEE Computer Society Edward J. McCluskey Technical Achievement Award.