Monday, March 2, 2015
Great America Meeting Room 3
Chair & Moderators:
Prof. Arijit Raychowdhury - Georgia Institute of Technology
Prof. Hai Li - University of Pittsburgh
Jim Dodrill - ARM
Prof. Gabriel A. Rincón-Mora - Georgia Tech
Dr. Tanya Nigam - GLOBALFOUNDRIES
Dr. Sandip Ray - Intel Corporation
Prof. Swarup Bhunia - Case Western
Prof. Hao Jiang - San Francisco State University
The Frontiers of Robust Circuit Design in Sub-28nm Process Technologies
Jim Dodrill, ARM
Summary: The major sources of margining and reliability concerns in integrated circuits are well known. They include timing uncertainty due to process, voltage and temperature variation; aging due to EM, NBTI/PBTI and HCI; and soft errors due to radiation. These concerns tend to increase as process geometries shrink, extreme dynamic voltage scaling is used to push frequencies up or drive power down, and operation across extended temperature ranges is required. Overly conservative design margins, which have been used in the past, have become too costly. EDA software to address these concerns is evolving, but not yet capable of accurately addressing all of them. So what is the state of the art in robust design and how much design margin is enough? This tutorial will attempt to answer those questions for applications ranging from servers to IoT devices using the latest literature and ARM's internal research and analysis.
About Jim Dodrill
Jim Dodrill is a Senior Principal Design Engineer in the Advanced Products Division of the Physical Design Group at ARM in Austin, TX. He is responsible for developing new standard cells and related methodologies in advanced process technologies that improve the power, performance, area, and yield possible with ARM Artisan© Physical IP, especially when used to implement ARM CPU and graphics cores. His recent work has focused on synchronizer design, on-chip variation, and soft error tolerance. Jim earned a Bachelor of Science in Electrical Engineering degree from Oklahoma State University and a Master of Science in Electrical Engineering and Computer Science degree from Duke University. His experience spans the range from custom transistor level design to full SOC chip tape-out and CAD enablement for companies including Texas Instruments, Ross Technology, and Analog Devices.
Prof. Gabriel A. Rincón-Mora , Georgia Tech
Summary:Wireless microsensors can not only monitor and manage power consumption in small- and large-scale applications for space, military, medical, agricultural, and consumer markets but also add energy-saving and life-saving intelligence to large infrastructures and tiny contraptions in remote and difficult-to-reach places. Ultra-small systems, however, cannot store sufficient energy to sustain monitoring, interface, processing, and telemetry functions for extended periods. And replacing or recharging the batteries of hundreds of networked nodes is prohibitive, and often impossible. This is why fuel cells, atomic batteries, and ambient sources are the subject of ardent research today. Except, power densities are low, and in some cases, intermittent, so these devices cannot power many functions. Plus, tiny lithium-ion batteries and super capacitors, while power dense, cannot sustain life for long. This talk illustrates how tiny fuel cells, batteries, and energy-harvesting generators can power practical microsystems for extended periods. For this, the presentation reviews prevailing system requirements, notes technological constraints, and shows the state of the art in miniaturized energy sources and power supplies.
About Prof. Gabriel A. Rincón-Mora
Prof. Gabriel A. Rincón-Mora worked for Texas Instruments in 1994-2003, was an Adjunct Professor at Georgia Tech in 1999-2001, and has been a Professor at Georgia Tech since 2001 and a Visiting Professor at National Cheng Kung University in Taiwan since 2011. He is a Fellow of the IEEE and IET, and his scholarly products include 9 books, 4 book chapters, 38 patents issued, over 160 publications, over 26 commercial power-chip designs, and over 95 invited talks. Awards include the National Hispanic in Technology Award from the Society of Professional Hispanic Engineers, the Charles E. Perry Visionary Award from Florida International University, a Commendation Certificate from the Lieutenant Governor of California, the IEEE Service Award from IEEE CASS, the Orgullo Hispano and the Hispanic Heritage awards from Robins Air Force Base, and two "Thank a Teacher" certificates from Georgia Tech. Georgia Tech inducted him into the Council of Outstanding Young Engineering Alumni in 2000 and Hispanic Business magazine named him one of "The 100 Most Influential Hispanics" in 2000. He has served as Distinguished Lecturer, General Chair, Technical Program Chair and Co-Chair, Associate Editor, Guest Editor and Co-Editor, and Chapter Chair and Vice-Chair on multiple occasions for IEEE, several international conferences, and several journal publications.
Reliability Challenges in Sub 20nm Technology
Dr. Tanya Nigam , GLOBALFOUNDRIES
Summary: It has been demonstrated that the introduction of HfO2 gate stacks into CMOS technologies provides the means to continue with traditional device gate length scaling. However, the introduction of HfO2 as a new gate dielectric into the gate stack of FETs brings about new challenges for understanding reliability physics and qualification. This tutorial summarizes recent advances in the modeling of charge trapping and defect generation in HfO2 gate stacks. The tutorial relates the electrical properties to the chemical/physical properties of the high-k dielectric and discusses implication for technology scaling. Additionally the reliability challenges with the introduction of new channel materials will be discussed.
About Dr. Tanya Nigam
Tanya Nigam is currently a Distinguished Member of Technical staff at GLOBALFOUNDRIES. After obtaining her PhD from IMEC in the area FEOL reliability she joined Bell Labs, Murray Hill. While at Bell Labs she worked on sub 50 nm device solution such as Vertical Replacement Gate. Later she worked on LDMOS reliability and device optimization. In 2005 she move to Cypress Semiconductors and worked on 65nm technology node. Since joining AMD in 2007 she has been working on all FEOL reliability mechanism starting from 45 nm. Her current work focus on defining reliability metric for future nodes and device to product correlation. She has been session chair at IRPS, IEDM and has more than 50 publications and 5 patents.
Secure Hardware in the Nano Era: Some New Directions
Prof. Swarup Bhunia , Case Western Reserve University
Summary: Security of electronics is traditionally associated with the security of software, the information being processed, and the network infrastructure. The hardware components, platforms and supply chains are considered secure and trustworthy. However, recent discoveries and reports on diverse security attacks in microchips and circuits violate the hardware root of trust. Protection against these attacks is extremely challenging due to economic issues as well as the sheer complexity of modern electronic hardware. To provide higher levels of assurance and trust to designers, system manufacturers and end users, there is an urgent need to integrate security measures during design and manufacturing test addressing all aspects of security threats. This presentation will cover some emerging solutions in this area. In particular, it will discuss low-overhead protection against counterfeiting attacks, system-on-chip security against side-channel attacks, hardware Trojan detection approaches and a novel paradigm for "design for security" (DfS) based on hardware obfuscation that can protect against malicious modifications as well as piracy. The talk would point to emerging threats and future directions in hardware security research.
About Prof. Swarup Bhunia
Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development experience with over 150 publications in peer-reviewed journals and premier conferences in the area of VLSI design, CAD and test techniques. His research interests include low power and robust electronics, hardware security and trust, adaptive nanocomputing and implantable/wearable microsystems. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IBM Faculty Award, National Science Foundation (NSF) career development award, Semiconductor Research Corporation (SRC) technical excellence award as a team member, several best paper awards and best paper nominations and SRC Inventor Recognition Award. He has served as an associate editor of IEEE Transactions on CAD and ACM journal of emerging technologies (JETC), guest editor of IEEE Design & Test of Computers, in the editorial board of Journal of Low Power Electronics (JOLPE) and in the program committee of number of IEEE/ACM conferences. He is a senior member of IEEE.
Security and Validation in SoC Designs Cooperation, Conflicts, and Trade-offs
Dr. Sandip Ray , Intel Corporation
Summary: Recent years have seen rapid proliferation of System-on-a-Chip (SoC) designs. SoC designs pervade in electronic devices for the embedded and global markets including smartphones, tablets, medical instruments, gaming, automotive, etc. The trend is towards even faster proliferation of these devices in the next decade with newer and more diverse form factors such as wearables and Internet-of-Things. One consequence of this diversity of critical applications is that security of the systems has become a centerpiece of SoC design, architecture, validation, and debug. Secure collaterals in a modern SoC design include secret keys, fuses, cryptographic modules, firmware, etc., and the design architecture includes complex security policies governing access to these collaterals during different phases of the system execution. Security validation in SoC designs entails ensuring both that the design implementation respects these policies, and that the policies themselves ensure the desired overall integrity of the system in the presence of adversaries. The "arms race" between increasing sophistication, diversity, of security attacks on the one hand and resiliency mechanisms in the design on the other, has made security validation a highly critical, complex, challenging, and fun activity. This tutorial will provide an overview of validation techniques for secure collaterals in SoC designs. We will consider security issues both at the level of individual IPs and for an integrated system, validation techniques at the different levels, and tradeoffs and challenges between IP-level and system-level strategies. We will also discuss conflicts and trade-offs between resiliency and validation techniques in the context of security collaterals. Specific examples of industrial validation practices will be discussed.
About Dr.Sandip Ray
Dr. Sandip Ray is a Research Scientist at the Strategic CAD Labs, Intel Corporation. His research focuses on developing correct, dependable, trustworthy, and secure computing systems through cooperation of specification, synthesis, verification, and validation techniques. At Intel, he leads a cross-collaborative research program, developing robust validation infrastructure for next-generation embedded devices. Before joining Intel, Dr. Ray worked as a Research Scientist at the University of Texas at Austin, where he developed analysis frameworks for diverse computing systems ranging from synthesized hardware designs to software routines including binary and assembly programs. His work found application in major semiconductor companies like AMD, Freescale, IBM, Intel, Galois, and Rockwell Collins. Dr. Ray is the author of three books (two upcoming), as well as more than 40 peer-reviewed research articles. He has served on the program committee of more than 20 international meetings and conferences, as co-chair for the International Conference on Formal Methods in Computer-Aided Design (FMCAD 2013) and International Workshop on the ACL2 Theorem Prover and Its Applications (ACL2 2009), as a guest editor for ACM Transactions on Design Automation of Electronic Systems (TODAES) and Springer Journal of Electronic Testing Theory and Applications (JETTA). Dr. Ray has a Ph.D. from the University of Texas at Austin, and is a senior member of IEEE.
Neuromorphic Computing based Processors
Prof. Hao Jiang , San Francisco State University
Summary: For implants that interfaces with neurons, a high-efficient miniaturized processor is highly desirable. Memristor based processor has demonstrated its potential to achieve high-efficient processing power with small factor, further, the spike based neuromorphic computing scheme has the potential to exchange information with neuron systems directly, since both systems rely on electrical spikes to deliver information. In such a system, however, the high-speed read and write circuits pose major challenge to its overall efficiency. Dr. Jiang and his students actively look for new circuit architectures to achieve efficient the read and write functions with maximal speed and minimal power and area. These circuits are different from traditional analog circuits because input and output signals swing from 0 to Vdd, also they are different from traditional digital circuits because the spacing time between any two spikes is a critical analog variable in the computation. A new breed of circuits is needed to achieve efficient signal processing with minimal power and size to meet implants' requirements.
About Prof. Hao Jiang
Hao Jiang received the B.S. degree in materials sciences from Tsinghua University, China, in 1994 and the Ph.D. degree in electrical engineering from the University of California, San Diego, in 2000. Hao Jiang has been with San Francisco State University since August 2007 as an assistant professor in electrical engineering. Prior joining SFSU, he worked for Broadcom Corporation, Jazz Semiconductor and Conexant Systems Inc. His research interests are in the general area of analog integrated circuits, particularly in ultra-low-power circuits for biomedical applications.