ISQED 2010 Tutorials
Monday, March 22, 2010
9:00am–5:00pm
Rooms: Carmel/Monterey
Chair & Moderator: Rajiv Joshi, IBM T J Watson Research Center
Beyond 32 nm Technology
K. Maitra
Global Foundries
In this tutorial, we explore the device design landscape beyond 32 nm technology and discuss its potential impact on design solutions. In particular, the potential of MUGFETs (Multi gate transistor architectures or its derivatives like FINFETs, or Trigates) as a potential device candidate for beyond 32 nm technology options would be discussed. Emphasis would be placed on design implications for SRAM and logic circuits. Two primary fabrication schemes based either on SOI or bulk substrates would be presented. Performance enhancement techniques like strain and (110) channel orientations would also be discussed. In the end, a simple cost benefit type analysis would be presented to evaluate the feasibility of design migration to beyond 32 nm technologies.
Energy Efficient Digital Circuit Design
Benton Calhoun
University of Virginia
This power limited era for circuits requires us to design digital systems with maximum energy efficiency. This talk describes a variety of emerging circuit and architecture techniques to improve energy efficiency across a broad range of application requirements in support of green computing.
At the ultra-low power (ULP) end of the application space, we motivate the use of sub-threshold operation for minimizing energy. We expand on previous circuit level work to show how properly leveraging sub-threshold circuits can dramatically lower energy consumption at the system level. These ULP techniques are enablers for distributed sensors that will become essential for tomorrow’s ubiquitous intelligent systems. For portable applications that require high performance operation at times, we discuss run-time circuit/architecture methods to trade off energy and performance in an efficient fashion.
Combining these methods with existing design time low power techniques can produce highly efficient green ICs. Finally, we examine efficiency issues related to SRAM design from high performance to embedded applications. We explore how circuit techniques can help overcome functionality challenges that result from scaling so that SRAM VDD can continue to decrease, thereby reducing power.
Alternate Memories
Stuart Parkin
IBM
Recent advances in generating, manipulating and detecting spin-polarized electrons and current make possible entire new classes of spin based sensor, memory and logic devices, technology generally referred to as the field of spintronics. A magnetic recording read head, based on the spin-valve, is the first example of a useful spintronic device, and enabled a 1,000-fold increase in the storage capacity of disk drives in just a few years after its introduction1. Even greater sensitivity is obtained by replacing the spin-valve, which is based on diffusive spin-dependent transport, with the magnetic tunnel junction, which uses spin-dependent tunnelling. This latter spintronic device also enables a high performance, non-volatile magnetic random access solid state memory1. The respective strengths of disk drives and memory, i.e. the very low cost of disk drives and the high performance and reliability of solid state memories, may be combined in the Racetrack Memory. The Racetrack Memory is a novel three dimensional technology which stores information as magnetic domain walls in magnetic nanowires and manipulates them using spin polarized current pulses2. Spintronic materials and devices may even be important for developing devices that mimic the operation of the synaptic switches in the brain.
SoC Verification
Ken Albin
Advanced Micro Devices
Functional verification has come to dominate the development time for System-on-Chip designs. As new technologies make more transistors available, design complexity increases and verification becomes even more difficult. This tutorial will provide an overview of the verification of System-on-Chip designs, covering: basics of functional verification, sources of complexity, what to verify, hierarchical verification, "trusted IP", quality metrics, the role of formal verification, and how to know when you are done. The role of relevant standards and new approaches will be identified and discussed.
Paving the Road for 3D TSV Design
Pol Marchal
IMEC
In this tutorial, we'll indicate the key design issues of a low-cost 3D Cu-TSV technology: impact of TSV on MOS devices and interconnect, reliability, thermal hot spots, ESD, signal integrity and impact on circuit performance. We will show experimental results, indicating their importance and offer solutions or propose changes in current design practices to enable low-cost systems.
Microprocessor Architecture Impact on Power
Dave Ayers
Intel
The talk will begin with an overview of trends in power consumption including the impact of mobile battery life and of Energy Star ratings. Then there will be an review some of the historical efforts to control power such as thermal throttling. He will progress to a brief review of power states and how they are used to reduce power in processors. Next, he will review where the power consumed in a typical processor. He will discuss some of the more specific techniques used to control power in today’s generation of processors including: power gating; independent voltage and frequency domains; adjusting voltage and frequency in response to processor loading and operating system state requests; making use of wide dynamic range; impacts to the system’s power delivery components; and interactions with other system components. Speaker will discuss some power control features which are of particular benefit to mobile, desktop, and server market segments. He will also go over how the increasing core count trend is affecting the power management landscape and creating opportunities for power/performance optimization for code with low thread counts and for code with low overall utilization. He will conclude by discussing how improved processor/system interaction will enable improved efficiency in future products.