Plenary Session 1P
8:45am–10:15am
Dr. Chi-Foon Chan
President & COO
Synopsys
Plenary Speech 1P.1: High Rel by Design - Creating Enterprise Class Memories
Ramanan ThiagarajahSr. Director of Product and Test Engineering
Inphi Corp
Enterprise class memory requirements are quickly outpacing the cost/density value curve. While DRAM $/bit is cheap, enabling high density solutions produces a technical and manufacturing challenge. With shorter product development and technology cycles for enterprise memory solutions, design quality and system integration is becoming increasingly important. The talk will take a holistic look at the role of DFm as it applies to product definition through end-of-life and the intricate balance between product robustness and time-to-market.
About Ramanan Thiagarajah
Ramanan Thiagarajah, as Director of Product & Test Engineering at Inphi, oversees new product introduction, manufacturing, strategic sourcing and product qualification across the breadth of Inphi products. Ramanan has over 13 years of experience in the semiconductor industry across a variety of functions spanning product/test engineering, applications engineering, marketing and business management. He started his career in 1998 at Vitesse Semiconductor. In mid-2001, he joined Inphi Corporation and helped structure the backend manufacturing process for both their Broadband Analog and Server & Storage businesses. Ramanan most recently was the product line manager for the Server & Storage business line at Inphi. Ramanan received his MBA with honors from the UCLA Anderson School of Management and his BSEE from the UCLA School of Engineering.
Plenary Speech 1P.2: The New Challenges of Advanced SoC Implementation
Shankar KrishnamoorthyChief Scientist, Place & Route Division
Mentor Graphics
With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SOCs. However, design challenges are growing as we push the limits of complexity, size, power reduction, and manufacturing scaling. These challenges, if left unaddressed, can result in an adverse impact to schedule and designer productivity. Designers need a new generation of physical design tools to effectively address issues such as multi-mode multi-corner design closure, optimization for low power, compensating for manufacturing variability and handling the sheer magnitude of billion-transistor designs. They also need tools that take advantage of the latest multi-core processors for rapid turnaround, and enable seamless chip assembly at the full-chip level. Mr. Krishnamoorthy’s talk will describe the new requirements for physical design tools and how innovative approaches can make designers successful in the era of “manufacturing aware” design. Examples from a variety of design applications, including HDTV, graphics and mobile processors illustrate this highly informative presentation
About Shankar Krishnamoorthy
Shankar Krishnamoorthy has over 18 years of experience in the EDA industry leading world-class R&D teams that have delivered the industry’s leading physical design and logic synthesis solutions. He is presently Chief Scientist of the Place & Route Division at Mentor Graphics Corp. where he oversees the research, development and deployment of Mentor’s P&R solutions. He joined Mentor Graphics in 2007 as a result of a merger with Sierra Design Automation, a provider of digital physical design solutions. At Sierra Design Automation, he was Founder , Chief Technical Officer and VP of Engineering. Under his leadership, Sierra successfully delivered a next-generation physical design solution, Olympus-SoC, that addressed many of the key design challenges at advanced process nodes. Prior to Sierra, Mr. Krishnamoorthy was at the helm of the Physical Synthesis R&D organization at Synopsys Inc. where he conceived, architected and delivered Physical CompilerTM, the industry-standard physical synthesis product, at the time. He also led the Design Compiler™ R&D group at Synopsys Inc., continually delivering the best logic synthesis technology in the industry. Mr. Krishnamoorthy received his Masters in Computer Science from University of Texas at Austin and Bachelors in Computer Science from Indian Institute of Technology, Bombay, India.
Plenary Speech 1P.3: Beyond Endless Verification: Delivering High Quality at Low Expense
Mark GogolewskiCTO & CFO
Denali Software
Everyone is familiar with the skyrocketing costs of verification. Denali Software faced the same challenge when tackling the verification of their configurable controller for PCI Express, one of the most complex and wide-spread interface protocols. As a commercial provider of IP, quality could not be sacrificed. At the same time, the business model could not support a huge design and verification team, nor wait forever. In this keynote, Denali CTO Mark Gogolewski will center on how a small group of talented, highly motivated engineers was able to consistently deliver one of the industry’s most complex IP cores, reliably and on-time.
About Mark Gogolewski
Mark Gogolewski, a 15-year veteran of the semiconductor industry, has served Denali in many capacities since co-founding the company in 1996. He oversees all of the company's finance and accounting activities and is directly responsible for controllership, tax, treasury, analysis, investor relations, internal controls, internal audit and financial operations. His extensive experience also includes leading the development of key simulation and verification technologies focused on advanced memory system design and verification and the industry's first configurable memory controller core solution. Mr. Gogolewski has a BS in Applied Mathematics and an MS in Engineering Physics from the University of Virginia.