International Symposium on Quality Electronic Design (ISQED)

New Approaches to Parasitic Extraction

Mentor GraphicsLunch Tutorial

Monday March 22, 2010

12 Noon–12:50pm

Room: Fir/Oak

Ramanan Thiagarajah Peter Shi Ramanan Thiagarajah Carey Robertson

Dr. Peter Shi, Ph.D., Development Engineering Director, Calibre Parasitic Extraction, Mentor Graphics
Carey Robertson, Director of Product Marketing, Mentor Graphics

At the 32/28 nm node, what were second-order device parasitics with minimal performance impact have now become first-order parasitics capable of degrading performance or generating operational failure. With a greater proportion of the layout requiring more precise extraction, rules-based extraction tools can no longer deliver the accuracy needed to confirm acceptable electrical performance. Higher accuracy has been achievable using “field solvers” that compute Maxwell’s equations in three dimensions for the target layout geometry. However, due to their long runtimes, field solvers have historically only been used in conjunction with test chips to calibrate “production” extraction tools that provide higher performance and throughput. What is now needed is a solution that meets both accuracy and run time requirements at 32nm and beyond. This session will describe the issues of extraction at advanced IC nodes, and describe commercial solutions that are being developed to address these issues.