International Symposium on Quality Electronic Design (ISQED)

ISQED'23 Keynotes

April 5, 2023

The Weakest Link: Microelectronics Security Against Physical Attacks

Domenic Forte Domenic Forte

Prof. Domenic Forte - University of Florida

For the past decade and a half, the hardware security community has expended significant time on threats related to semiconductor globalization. With the passage of the CHIPS Act in the US and similar legislation around the world, untrusted foundries should no longer be considered the weakest link. It is time to refocus efforts towards physical attacks against microelectronics. Physical attacks exist across a wide spectrum – from low-cost/low-reward non-invasive attacks to high-cost/high-reward invasive attacks – and have successfully extracted on-chip assets and broken roots-of-trust in recent years. Some non-invasive attacks have even found success remotely. Further, the threat of semi-invasive attacks, such as optical probing, is growing. Semi-invasive attacks are low in cost like non-invasive attacks but nearly as powerful as invasive attacks. This keynote will review this dangerous landscape and discuss emerging approaches that bolster physical security. It is said that “Time is what determines security. With enough time nothing is unhackable.” Hence, more attention will be paid to techniques that quantifiably increase the time and complexity of physical attacks.


About Domenic Forte

Domenic Forte is an Associate Professor and the Steven A. Yatauro Faculty Fellow with the Electrical and Computer Engineering Department at University of Florida. He is also Associate Director for the Florida Institute for National Security (FINS). His research covers the domain of hardware security from transistors to printed circuit boards where he has over 200 publications. Dr. Forte is a senior member of the IEEE, a member of the ACM, and serves or has served on the technical program committees of leading events such as USENIX Security, NDSS, HOST, ASHES, DAC, ICCAD, ITC, ISTFA, and BTAS. Dr. Forte is a recipient of the Presidential Early Career Award for Scientists and Engineers (PECASE), the NSF CAREER Award, and the ARO Young Investigator Award. His research has also been recognized with best paper awards and nominations from IJCB, ISTFA, HOST, DAC, and AHS. For teaching and advising, he has received the Herbert Wertheim College of Engineering Doctoral Dissertation Advisor/Mentoring Award, the Excellence in Teaching Award from UF’s ECE Graduate Student Organization, and the George Corcoran Outstanding Teaching Award from University of Maryland.

Future Directions for Simulation-Driven Product Innovation

Prith Banerjee Prith Banerjee

Dr. Prith Banerjee - Chief Technology Officer, ANSYS

In the past, customers used to create innovative products by building a hardware prototype of the product, testing the prototype under different operating conditions, refining the prototype, and finally manufacturing the product at scale. That process was long, costly, and error-prone. Increasingly, our customers are using computer-aided design and computer-aided engineering simulation to build software prototypes of the product and performing virtual validation. In this talk I will provide an overview of some future technology directions of simulation-based product innovation around five pillars: (1) Numerical methods and models (2) High-Performance Computing (3) Artificial intelligence and Machine Learning (4) Cloud, Platforms and User Experience and (5) Digital Engineering. The future of product innovation in the connected world is very exciting in industries as diverse as high-tech and semiconductors, aerospace and defense, automotive and transportation, energy and industrials, and healthcare.


About Prith Banerjee

Prith Banerjee is Chief Technology Officer at ANSYS, a leader in engineering simulation. Prior to that, he CTO of Schneider Electric, CTO of ABB, Managing Director of R&D at Accenture, and Director of HP Labs. Previously he spent 20 years in academia as Professor, Chairman and Dean at the University of Illinois and Northwestern University. Banerjee currently serves on the Board of Directors of Turntide. In the past, he has served on the Board of Cray, CUBIC. and Anita Borg Institute. He is a Fellow of the AAAS, ACM and IEEE. He received a B.Tech. in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana.

April 6, 2023

Pushing the Energy-efficiency of Deep Learning Accelerators with Hardware-Software Co-design

Rangharajan Venkatesan Rangharajan Venkatesan

Dr. Rangharajan Venkatesan - Senior Research Scientist , NVIDIA

Deep neural networks (DNNs) have emerged as a key approach to solving complex problems across many application spaces, including image recognition, natural language processing, robotics, health care, and autonomous driving. Designing custom hardware accelerators for deep neural networks is highly promising, as they offer significant performance and power advantages compared to general-purpose processors. This talk presents MAGNet, a hardware-software co-design framework that explores different data formats, quantization techniques, memory hierarchies, and dataflows. This talk describes a new data format VS-Quant for achieving low-precision computation and novel multi-level dataflows to improve energy efficiency.


About Rangharajan Venkatesan

Rangharajan Venkatesan is a Senior Research Scientist in the ASIC & VLSI Research group in NVIDIA. He received the B.Tech. degree in Electronics and Communication Engineering from the Indian Institute of Technology, Roorkee in 2009 and the Ph.D. degree in Electrical and Computer Engineering from Purdue University in August 2014. His research interests are in the areas of low-power VLSI design and computer architecture with a particular focus in deep learning accelerators. He has received Best Paper Awards for his work on deep learning accelerators from IEEE/ACM Symposium on Microarchitecture (MICRO) and Journal of Solid-State Circuits (JSSC). His work on spintronic memory design was recognized with the Best Paper Award at the International Symposium on Low Power Electronics and Design (ISLPED), and Best paper nomination at the Design, Automation and Test in Europe (DATE). His paper titled, “MACACO: Modeling and Analysis of Circuits for Approximate Computing”, received the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Ten Year Retrospective Most Influential Paper Award in 2021. He has served as a member of the technical program committees of several leading IEEE/ACM conferences including ISSCC, DAC, MICRO, and ISLPED.