ISQED'22 Embedded Tutorials
Chair & Moderators:
José Pineda de Gyvez - NXP Semiconductors (Chair)
Yu Pu - HASH innovation center, BITMAIN Inc.(Co-Chair)
Tutorial 1
Wednesday, April 6, 11:35AM-12:35PM
Neuromorphic processing at the sensor edge: Engineering tiny brain
Presenter:
Amir Zjajo , Innatera Nanosystems
Amir Zjajo Abstract: Brain-inspired, neuromorphic spiking neural network emulators form distributed, parallel, and event-driven system offering signal transmission energy-efficiency, and intelligence or inference capabilities to resource-constrained devices. Computational elements of the reconfigurable neuromorphic networks, typically, only partially include dendritic, and subsequently, synaptic properties. However, increased experimental evidence indicates the existence of a large diversity of dendritic channels, which modify synaptic response by amplification, regulation, the dendritic structure scaling, etc. We abstract the fundamental dendritic functions by extracting the underlying dynamics governed by bio-chemical processes; this increase in dimensionality allows more states and transitions (and time constants), offering more flexibility in the implementation of plastic and metaplastic interactions, i.e. providing mechanism to realize and maintain robust neural computation, in addition to enhancing specifics of the sensory signal processing, e.g. accentuate changes in stimulus parameters, prevent spiking frequency saturation, tune frequency responses to specific stimulus features. In this tutorial, we address several important questions such as i) how do we leverage all the advantages of dendritic bio-chemical signal processing at different levels of time-granularity or hierarchy, and ii) how the main principles of a tiny-brain translate to competitive (sub-pJ level synaptic operation) neuromorphic hardware platforms, and software/hardware co-alignment in terms of distributed processing, technological variability, and neural network definitions and mapping. Enabling such paradigms and concepts open in-roads towards several high-potential use-cases geared specifically towards processing incoming data in an always-on, event-driven fashion facilitating truly smart-sensing and energy-optimized sensor systems.
About Amir Zjajo
Amir Zjajo is co-founder of Innatera Nanosystems B.V., and serves as its Chief Scientist. Prior to that, he was a member of research staff in the Mixed Signal Circuits and Systems Group at Philips Research Laboratories between 2000 and 2006, and subsequently, with Corporate Research at NXP Semiconductors until 2009. He joined the Delft University of Technology the same year, and was responsible for leading research into intelligent systems within a range of EU-funded research projects. Dr. Zjajo has authored 3 books, and published more than 90 papers in referenced journals and conference proceedings in the areas of mixed-signal VLSI design, and neuromorphic circuits and systems. He received the M.Sc. and DIC degrees from the Imperial College London, London, U.K., in 2000, and the PhD. degree from Eindhoven University of Technology, Eindhoven, The Netherlands in 2010, all in electrical engineering. His research interests include energy-efficient circuit and system design for on-chip machine learning and inference, and bionic electronic circuits for autonomous cognitive systems. Dr. Zjajo won best/excellence paper award at BioDevices’15 and LifeTech’19. He is a senior member of IEEE.
Tutorial 2
Thursday, April 7, 1:05PM-2:05PM
Analog, Mixed Signal and Power Integrated Circuits (ICs) for automotive applications and testing methodology for quality
Presenter:
Sri Navaneeth Easwaran, Texas Instruments Inc, Dallas, TX, USA (Speaker)
Robert Weigel, University of Erlangen-Nuremberg, Erlangen, Germany
(Co-Author)
Robert Weigel
Sri Navaneeth EaswaranAbstract: Power transistors form the main component of automotive Integrated Circuits (ICs) and they handle several amperes of current (>2A). State of the Art is to integrate several power MOSFETs along with their gate drivers (including charge pumps or boost converters that supply the gate drivers) whose operating voltage range is from 5V to 60V. Reliability of these integrated gate drivers and power transistors is a key factor to meet the high-quality demands of the automotive applications. In this tutorial, challenges related to the design and reliability of circuits like LDOs, High Side (HS) drivers, Low Side (LS) drivers and configurable HS/ LS drivers are discussed along with information related to floating nodes, aging and reliability related concerns like NBTI/PBTI, HCI etc. and proven design techniques to simulate and mitigate these challenges. These gate drivers have to be thoroughly designed for robustness w.r.to. Electrical and Thermal Safe Operating Area (SOA) and its test methodology by shorting the outputs to ground and battery will be discussed. In this tutorial, Design FMEA (Failure Mode Effect Analysis) based analysis to mitigate risks at design and system level along with test concepts towards very low dppm (defective parts per million) will be discussed. This tutorial will be valuable for the design, product and test engineers developing ICs for automotive and industrial applications.
About Sri Navaneeth Easwaran
Dr. –Ing. Sri Navaneeth Easwaran, Senior Member IEEE, received his Bachelor’s (1998, Bharathidasan University), Master’s (2006, University Twente) degrees in Electrical Engineering and Dr. –Ing. degree from University of Erlangen-Nuremberg in 2017. He worked at SPIC Electronics, STMicroelectronics, Philips Semiconductors between 1998 and 2006. From 2006 he is with Texas Instruments (TI) where he was the design lead of airbag squib driver ICs. and System Basis Chips. He is an IET Fellow (Feb 2021), TI Senior Member Technical Staff, has 20+ granted patents and 14 publications. He has offered tutorials on automotive ICs at IEEE Conferences. Since Dec 2020, he is offering iDLP (Industrial Distinguished Lecturer Program) CASS seminars on smart automotive circuits.
About Robert Weigel
Dr. -Ing. Dr.-Ing. habil. Robert Weigel, Fellow IEEE and Fellow ITG, is Full Professor at the University of Erlangen-Nuremberg, Germany. He co-founded several companies some of which were later overtaken by Infineon,
Intel and Apple, respectively. He has been engaged in microwave electronic circuits and systems and has published more than 1200 papers. He received the 2002 VDE ITG-Award, the 2007 IEEE Microwave Applications Award, the 2016 IEEE MTT-S Distinguished Educator Award, the 2018 Distinguished Service Award of the EuMA and the 2018 IEEE Rudolf Henning Distinguished Mentoring Award. He has been Distinguished Microwave Lecturer, MTT-S AdCom Member, and the 2014 MTT-S President.