Dr. Chi-Foon Chan - co-CEO, Synopsys
Dr. Chi-Foon Chan, co-CEO of Synopsys, discusses ways in which the technology landscape is shifting in response to a variety of external factors. From supply chain uncertainties to geopolitical issues and cyber security threats, the semiconductor industry is forced to constantly adjust both business practices and technology itself to move forward. In a time where change is constant, maintaining trust in our partnerships and alliances is paramount in supporting widespread adoption of new methods and devices. Dr. Chan touches on these themes and how trust becomes our biggest asset in a new era of tech.
About Chi-foon Chan
As Synopsys' co-CEO, Chi-Foon Chan shares responsibility for crafting vision and strategy, leading the company, and ensuring execution excellence in support of our customers' success. He has also served as the company's President and COO, a role he held for 14 years prior to his 2012 appointment to President and co-CEO, where he guided internal operations and worldwide field organizations. Chi-Foon joined Synopsys in 1990 as Vice President of Applications and Services, where he helped build the Technical Field organization. He has sponsored several key initiatives such as entering the IP market, and he personally facilitated key acquisitions such as Avanti, Virage Logic, Magma Design Automation, and SpringSoft. In 2014 he led Synopsys' entry into the software testing market with the acquisition of Coverity, and into the software security market with the acquisition of Codenomicon. Prior to Synopsys, Chi-Foon contributed to industry-leading companies like NEC Corporation, where he was General Manager of the Microprocessor Group, responsible for marketing all NEC chip devices in North America. Prior to NEC, he was an engineering manager at Intel Corporation. He holds an M.S. and a Ph.D. in Computer Engineering from Case Western Reserve University and a B.S. in Electrical Engineering from Rutgers University.
Jeff Dyck, Senior Director of Engineering, Siemens EDA
Machine learning methods are effective at cutting down verification runtimes and increasing coverage - it is common to see 2X-1000X improvements in these areas. In practice, these speedups are often too good to be true, as they come with questionable accuracy, where they can give incorrect answers without being able to tell. These fast, but inaccurate verification methods are not suitable for verifying engineering designs, and end up being no more than cool demos, with no practical application. This talk reviews a suite of proven techniques used in Solido's verification tools for meeting specific accuracy criteria and proving that the answer is correct, while still delivering big machine learning speedups.
About Jeff Dyck
Jeff Dyck is Senior Director of Engineering at Siemens EDA, responsible for R&D for three software product lines in the integrated circuit verification solutions (ICVS) division. Prior to joining Siemens, Jeff was VP of Engineering at Solido Design Automation, where he led Solido's R&D teams, managed Solido’s product lines, and co-invented Solido’s machine learning technologies. Solido was acquired by Siemens in 2017. Jeff is now working on evolving the active learning technology in Solido's products, as well as developing new disruptively differentiated tools within the Siemens EDA analog mixed signal product line.
Prof. Eby G. Friedman - University of Rochester
The scaling of semiconductor CMOS technology is now approaching fundamental physical limitations, encouraging the development of novel beyond-CMOS emerging technologies to supplement existing electronic systems. One rapidly growing application area for these beyond-CMOS circuits is energy efficient, large scale stationary computing – data centers and supercomputers. A particularly appropriate technology for this important application is superconductive electronics; in particular, single flux quantum (SFQ) circuits - the most widely adopted superconductive digital logic family. This technology exhibits speeds in the tens to hundreds of gigahertz while dissipating 100 to 1000X less power than CMOS. The fabrication capabilities of modern superconductive foundries currently approach a million logic gates per integrated circuit. Algorithms and methodologies aware of the issues posed by the large scale integration of SFQ circuits are topics of great currency. In this lecture, superconductive electronic circuits are introduced, and issues and solutions to enable the large scale integration of complex SFQ integrated circuits and systems are presented. Particular emphasis is placed on the many challenges faced by modern superconductive logic circuits and large scale digital systems. Among these issues are compact and efficient cryogenic memory, synchronization of sub-terahertz digital systems, interconnect routing, energy efficient current bias networks, and design for testability. Single flux quantum circuits are capable of transforming large scale computing systems - an increasingly important application due to the movement of data storage and processing onto remote cloud servers. Models, circuits, algorithms, and design methodologies to enable the development of next generation, large scale SFQ systems are the primary topics of this presentation.
About Eby G. Friedman
Eby G. Friedman received the B.S. degree in electrical engineering from Lafayette College and the M.S. and Ph.D. degrees in electrical engineering from the University of California at Irvine. He was with Hughes Aircraft Company from 1979 to 1991, rising to Manager of the Signal Processing Design and Test Department, where he was responsible for the design and test of high performance digital and analog ICs. He has been with the Department of Electrical and Computer Engineering, University of Rochester since 1991, where he is a Distinguished Professor and the Director of the High Performance VLSI/IC Design and Analysis Laboratory. He is also a Visiting Professor with the Technion — Israel Institute of Technology. He has authored almost 600 papers and book chapters, 24 patents, and authored or edited 19 books in the fields of high speed and low power CMOS design techniques, 3-D design methodologies, high speed interconnect, superconductive circuits, and the theory and application of synchronous clock and power distribution networks. His current research and teaching interests include high performance synchronous digital and mixed-signal circuit design and analysis with application to high speed portable processors, low power wireless communications, and server farms. Dr. Friedman is a recipient of the IEEE Circuits and Systems Mac Van Valkenburg Award, the IEEE Circuits and Systems Charles A. Desoer Technical Achievement Award, the University of Rochester Graduate Teaching Award, and the College of Engineering Teaching Excellence Award. He was the Editor-in-Chief and Chair of the steering committee of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Editor-in-Chief of the Microelectronics Journal, Regional Editor of the Journal of Circuits, Systems and Computers, an editorial board member of numerous journals, and a program and technical chair of several IEEE conferences. He is an IEEE Fellow, Senior Fulbright Fellow, National Sun Yat-sen University Honorary Chair Professor, and an inaugural member of the UC Irvine Engineering Hall of Fame.