Chair: Yang Yi, University of Kansas
Co-Chair: Hai (Helen) Li, Duke University

10:25AM
1A.1
Electrical Modeling and Analysis of 3D Synaptic Array using Vertical RRAM Structure
Hongyu An¹, M. Amimul Ehsan¹, zhen zhou², Yang Yi^1
1University of Kansas, ²Intel Corporation

10:45AM
1A.2
SRAM Voltage Scaling for Energy-Efficient Convolutional Neural Networks
Lita Yang and Boris Murmann
Stanford University

11:05AM
1A.3
Stochastic-Based Multi-Stage Streaming Realization of Deep Convolutional Neural Network
Mohammed Alawad¹ and Mingjie Lin^2
1PhD student at UCF, ²University of Central Florida

11:25AM
1A.4
A Fast and Ultra Low Power Time-Based Spiking Neuromorphic Architecture for Embedded Applications
Tao Liu¹ and Wujie Wen^2
1ECE Department, Florida International University, ²Florida International University

Chair: Sumeet Kumar Gupta, Penn State University
Co-Chair: Jack Sampson, Penn State University

10:25AM
1B.1
Circuit Design for Beyond Von Neumann Applications Using Emerging Memory: From Nonvolatile Logics to Neuromorphic Computing
Meng-Fan (Marvin) Chang¹, Wei-Hao Chen¹, Win-San Khwa¹, Jun-Yi Li¹, Wei-Yu Lin¹, Huan-Ting Lin¹, Yongpan Liu², Yu Wang², Huaqiang Wu², Huazhong Yang^2
1National Tsing Hua University, ²Tsinghua University

10:45AM
1B.2
Harnessing Ferroelectrics for Non-volatile Memories and Logic
Sumeet Gupta¹, Danni Wang², Sumitha George², Ahmedullah Aziz², Xueqing Li², Suman Datta³, Vijaykrishnan Narayanan^2
1The Pennsylvania State University, ²Penn State University, ³University of Notre Dame

11:05AM
1B.3
Test Challenges in Embedded STT-MRAM Arrays
Insik Yoon and Arijit Raychowdhury
Georgia Institute of Technology

11:25AM
1B.4
Evaluating Tradeoffs in Granularity and Overheads in Supporting Nonvolatile Execution Semantics
Kaisheng Ma, Minli (Julie) Liao, Xueqing Li, Zhixuan Huan, John (Jack) Sampson
Penn State

Chair: Jayita Das, INTEL
Co-Chair: Swatilekha Saha, Cypress Semiconductor Corporation

10:25AM
1C.1
Communication Limits of On-Chip Graphene Plasmonic Interconnects
Shaloo Rakheja
New York University

10:45AM
1C.2
Variation-Immune Resistive Non-Volatile Memory using Self-Organized Sub-Bank Circuit Designs
Navid Khoshavi, Soheil Salehi, Ronald F. DeMara
University of Central Florida

11:05AM
1C.3
Constructing Fast and Energy Efficient 1TnR based ReRAM Crossbar Memory
Lei Zhao¹, Lei Jiang², Youtao Zhang¹, Nong Xiao³, Jun Yang^1
1University of Pittsburgh, ²Indiana University Bloomington, ³National University of Defense Technology

11:25AM
1C.4
Learning to Trust an Emerging Technology: The Molecular Field Coupling Nanocomputing Case Study
Mariagrazia Graziano¹, Ruiyu Wang¹, Marco Vacca¹, Fabrizio Riente¹, Giovanna Turvani¹, Franco Cacialli², Gianluca Piccinini^3
1Politecnico di Torino, ²University College London, ³Politecnico di Torino, University College London

Chair: Kurt Schwartz, Texas Instruments, Inc.
Co-Chair: Raviprakash Rao, Texas Instruments, Inc.

3:55PM
2A.1
Re-addressing SRAM Design and Measurement for Sub-threshold Operation in View of Classic 6T vs. Standard Cell Based Implementations
Xin Fan¹, Jan Stuijt¹, Rui Wang¹, Bo Liu¹, Tobias Gemmeke^2
1Holst-Centre / imec, ²RWTH Aachen University

4:15PM
2A.2
Tunnel FET Based Ultra-Low-Leakage Compact 2T1C SRAM
Navneet Gupta¹, Adam Makosiej², Amara Amara³, Andrei Vladimirescu³, Costin Anghel^4
1Institut supérieur d'électronique de Paris, France; LETI, Commissariat à l’Energie Atomique et aux Energies Alternatives (CEA-LETI) France;, ²LETI, Commissariat à l'énergie atomique et aux énergies alternatives (CEA-LETI) France, ³Institut supérieur d'électronique de Paris, ⁴ISEP

4:35PM
2A.3
Low Redundancy Matrix-Based codes for Adjacent Error Correction with Parity Sharing
Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao
Harbin Institute of Technology

4:55PM
2A.4
0.6 V operation, 16 % Faster Set/Reset ReRAM Boost Converter with Adaptive Buffer Voltage for ReRAM and NAND Flash Hybrid Solid-State Drives
Kota Tsurumi, Masahiro Tanaka, Ken Takeuchi
Chuo university

Chair: Vivek Joshi, GLOBALFOUNDRIES
Co-Chair: Jayita Das, INTEL

3:55PM
2B.1
Low Temperature Endurance Failures on Flash Memory
Steve Heinrich-Barna¹, Clyde Dunn¹, Douglas Verret^2
1Texas Instruments, Inc, ²Texas Instruments, Inc (Retired)

4:15PM
2B.2
Virtual Characterization for Exhaustive DFM Evaluation of Logic Cell Libraries
Samuel Pagliarini, Mayler Martins, Lawrence Pileggi
Carnegie Mellon University

4:35PM
2B.3
Overview and development of EDA tools for integration of DSA into patterning solutions
Andres Torres, Germain Fenger, Daman Khaira, Yuansheng Ma, Yuri Granik, Chris Kapral, Joydeep Mitra, Polina Krasnova
Mentor Graphics Corporation

4:55PM
2B.4
Performance- and Energy-Aware Optimization of BEOL Interconnect Stack Geometry in Advanced Technology Nodes
Kwangsoo Han, Andrew Kahng, Hyein Lee, Lutong Wang
UCSD

Chair: Steve Heinrich-Barna, Texas Instruments, Inc.
Co-Chair: Vinod Viswanath, Real Intent

5:15PM
P1
A Technique to Construct Global Routing Trees for Graphene Nanoribbon (GNR)
Subrata Das and Debesh Kumar Das
Jadavpur University

5:15PM
P2
Regularized Logistic Regression for Fast Importance Sampling Based SRAM Yield Analysis
Lama Shaer¹, Rouwaida Kanj¹, Rajiv Joshi², Maria Malik³, Ali Chehab^1
1American University of Beirut, ²IBM, ³George Mason University

5:15PM
P3
Binary Adder Circuit Design Using Emerging MIGFET Devices
Jeferson Baqueta, Felipe Marranghello, Augusto Neutzling, Vinicius Neves Possani, André Inacio Reis, Renato Perez Ribas
UFRGS

5:15PM
P4
A Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures
Sungkwan Ku¹, Elliott Forbes², Rangeen Basu Roy Chowdhury³, Eric Rotenberg^4
1North Carolina State University, ²University of Wisconsin - La Crosse, ³Intel, ⁴North Carolina State University / Qualcomm

5:15PM
P5
Energy Efficient Analog Spiking Temporal Encoder with Verification and Recovery Scheme for Neuromorphic Computing Systems
Chenyuan Zhao, Jialing Li, Hongyu An, Yang Yi
University of Kansas

5:15PM
P6
3D-NOCET: A Tool for Implementing 3D-NoCs based on The Direct-Elevator Algorithm
maha Beheiry¹, Hassan Mostafa², Ahmed M. Soliman^2
1Mentor Graphics, ²Cairo University

5:15PM
P7
Design Technology Co-Optimization of Back End of Line Design Rules for a 7 nm Predictive Process Design Kit
Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence Clark
Arizona State University

5:15PM
P8
Investigation of Magnetic Field Attacks on Commercial Magneto-Resistive Random Access Memory
Alexander Holst¹, Jae-Won Jang², Swaroop Ghosh^2
1University of South Florida, ²Pennsylvania State University

5:15PM
P9
A 13T Radiation-Hardened Memory Cell for Low-Voltage Operation and Ultralow Power Space Applications
Chunhua Qi, Liyi Xiao, Mingxue Huo, Tianqi Wang, Rongsheng Zhang, Xuebing Cao
harbin institute of technology

5:15PM
P10
A New Approach for Selecting Inputs of Logic Functions During Debug
Amir Masoud Gharehbaghi¹ and Masahiro Fujita^2
1The University of Tokyo, ²University of Tokyo

5:15PM
P11
Fast and Energy-Aware Resource Provisioning and Task Scheduling for Cloud Systems
Hongjia Li¹, Ji Li², Wang Yao³, Shahin Nazarian², Xue Lin⁴, Yanzhi Wang^1
1Syracuse University, ²University of Southern California, ³High School in China, ⁴Northeastern University

5:15PM
P12
Evaluating the Benefits of a Relaxed BEOL Pitch for Deeply Scaled ICs
Mehmet M Isgenc, Samuel Pagliarini, Renzhi Liu, Larry Pileggi
Carnegie Mellon University

5:15PM
P13
STA Compatible Backend Design Flow for TSV-based 3-D ICs
Harry Kalargaris, Yi-Chung Chen, Vasilis Pavlidis
University of Manchester

5:15PM
P14
Off-Chip Test Architecture for Improving Multi-Site Testing Efficiency using Tri-State Decoder and 3V-Level Encoder
Sungyoul Seo¹, Hyeonchan Lim¹, Soyeon Kang¹, Sungho Kang^2
1Yonsei University, Seoul, Korea, ²Yonsei University

5:15PM
P15
Determining Proximal Geolocation of IoT Edge Devices via Covert Channel
Md Nazmul Islam, Vinay C Patil, Sandip Kundu
University of Massachusetts Amherst

Chair: Vinod Viswanath, Real Intent
Co-Chair: Anand Iyer, Microsoft

09:00AM
3A.1
Clock tree optimization through selective airgap insertion
Daijoon Hyun, Wachirawit Ponghiran, Youngsoo Shin
KAIST

09:20AM
3A.2
An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops
Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens
Eindhoven University of Technology

09:40AM
3A.3
High Sigma Statistical Hold Time Analysis in FinFET Sequential Circuits
Sam Lo, Taylor Lee, Aaron Barker
Oracle

10:00AM
3A.4
Power Prediction of Embedded Scalar and Vector Processor: Challenges and Solutions
Vijay Kiran Kalyanam¹, Peter Sassone², Jacob Abraham^3
1Qualcomm Technologies, Inc., ²Qualcomm Technologies Inc., ³CERC, The University of Texas at Austin

10:20AM
3A.5
Power-Delay Product Based Resource Library Construction for Effective Power Optimization in HLS
Shantanu Dutt¹ and Ouwen Shi^2
1University of Illinois at Chicago, ²Univ. of Illinois at Chicago

Chair: Swaroop Ghosh, Penn State University
Co-Chair: Gang Qu, University of Maryland

09:00AM
3B.1
Crossover Ring Oscillator PUF
Zihan Pang¹, Jiliang Zhang², Qiang Zhou³, Shuqian Gong², Xu Qian¹, Bing Tang^4
1China University of Mining & Technology (Beijing), ²Northeastern University, China, ³Tsinghua University, ⁴Guangdong Eshore Science and Technology Co., Ltd

09:20AM
3B.2
Integrated Circuit Identification and True Random Numbers using 1.5-Transistor Flash Memory
Lawrence Clark, James Adams, Keith Holbert
Arizona State University

09:40AM
3B.3
Methodologies to Exploit ATPG Tools for De-camouflaging
Deepakreddy* Vontela¹ and Swaroop Ghosh^2
1University of South florida, ²Pennsylvania State University

10:00AM
3B.4
Low-Overhead Implementation of Logic Encryption Using Gate Replacement Techniques
Xiaoming Chen¹, Qiaoyi Liu¹, Yu Wang¹, Qiang Xu², Huazhong Yang^1
1Tsinghua University, ²The Chinese University of Hong Kong

10:20AM
3B.5
Scan Chain based IP Fingerprint and Identification
Xi Chen¹, Gang Qu¹, Aijiao Cui², Carson Dunbar^1
1University of Maryland, ²Harbin Institute of Technology Shenzhen Graduate School

Chair: Payman Zarkesh-Ha, University of New Mexico
Co-Chair: Vivek Joshi, GLOBALFOUNDRIES

09:00AM
3C.1
Performance-Thermal Trade-offs for a VFI-Enabled 3D NoC Architecture
Dongjin Lee, Sourav Das, Partha Pande
Washington State University

09:20AM
3C.2
A Legalization Algorithm for Multi-Tier Gate-Level Monolithic Three-Dimensional Integrated Circuits
Yiting Chen and Dae Hyun Kim
Washington State University

09:40AM
3C.3
Cooling Architectures using Thermal Sidewalls, Interchip Plates, and Bottom Plate for 3D ICs
Kaoru Furumi, Masashi Imai, Atsushi Kurokawa
Hirosaki University

10:00AM
3C.4
High Performance Virtual Channel Based Fully Adaptive Thermal-aware Routing for 3D NoC
Xin Jiang, Xiangyang Lei, Lian Zeng, Takahiro Watanabe
Graduate School of Information, Production & Systems, Waseda University

10:20AM
3C.5
Data Interface Buffer Compensation Scheme for Fast Calibration
Sameer Shekhar, Amit Kumar Jain, Pooja Nukala
Intel Corporation

Chair: Shivam Bhasin, Nanyang Tech. University
Co-Chair: Anupam Chattopadhyay, Nanyang Tech. University

10:50AM
4A.1
Chosen-Input Side-Channel Analysis on Unrolled Light-Weight Cryptographic Hardware
Ville Yli-Mäyry, Naofumi Homma, Takafumi Aoki
Tohoku University

11:10AM
4A.2
An Electromagnetic Fault Injection Sensor using Hogge Phase-Detector
Wei He, Jakub Breier, Shivam Bhasin
Nanyang Technological University

11:30AM
4A.3
FPGA Implementation of Modeling Attack Resistant Arbiter PUF with Enhanced Reliability
Siarhei S. Zalivaka¹, Alexander A. Ivaniuk², Chip Hong Chang^1
1Nanyang Technological University, ²Belarusian State University of Informatics and Radioelectronics

11:50AM
4A.4
Towards Lightweight Identity-Based Encryption for the Post-Quantum-Secure Internet of Things
Tim Güneysu¹ and Tobias Oder^2
1University of Bremen & DFKI, ²Ruhr-Universität Bochum

12:10PM
4A.5
SHA-3 Implementation Using ReRAM based In-Memory Computing Architecture
Debjyoti Bhattacharjee, Vikramkumar Pudi, Anupam Chattopadhyay
Nanyang Technological University

Chair: Libor Rufer, University Grenoble-Alpes, France
Co-Chair: Kamesh Gadepally, GigaCom Semiconductor

10:50AM
4B.1
A Hybrid RFID and CV System for Item-Level Localization of Stationary Objects
Everton Berz, Deivid Tesch, Fabiano Hessel
PUCRS University

11:10AM
4B.2
Energy Efficient Biopotential Acquisition Unit for Wearable Health Monitoring Applications
Wazir Singh, Yatharth Gupta, Paritosh Jivani, Sujay Deb
IIIT Delhi

11:30AM
4B.3
Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice
Leo Filippini¹, Diane Lim², Lunal Khuon¹, Baris Taskin^1
1Drexel University, ²University of Pennsylvania

11:50AM
4B.4
CAP: Configurable Resistive Associative Processor for Near-Data Computing
Mohsen Imani¹ and Tajana Rosing^2
1University of California San Diego, ²UCSD

12:10PM
4B.5
Low-power MEMS-based sensors
David Horsley
University of California, Davis

Chair: Vivek Nandakumar, Cadence Design Systems
Co-Chair: Steve Heinrich-Barna, Texas Instruments, Inc.

10:50AM
4C.1
Performance Evaluation of Copper and Graphene Nanoribbons in 2-D NoC Structures.
Ruturaj Pujari and Shaloo Rakheja
New York University

11:10AM
4C.2
Processor/Memory Co-scheduling Using Periodic Resource Server for Real-Time System Under Peak Temperature Constraints
Gustavo A. Chaparro-Baquero, Shi Sha, Soamar Homsi, Wujie Wen, Gang Quan
Florida International University

11:30AM
4C.3
Data Center Power Management for Regulation Service Using Neural Network-Based Power Prediction
Ning Liu¹, Xue Lin², Yanzhi Wang^1
1Syracuse University, ²Northeastern University

11:50AM
4C.4
An Energy Efficient Non-uniform Last Level Cache Architecture in 3D Chip-Multiprocessors
pooneh safayenikoo¹, Arghavan Asad², Mahmood Fathy², Farah Mohammadi^3
1School of Computer Engineering, iran university of science and technology, ²Iran University of Science and Technology, ³Ryerson University

12:10PM
4C.5
Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors
Scott Lerner and Baris Taskin
Drexel University

Chair: Kurt Schwartz, Texas Instruments, Inc.
Co-Chair: Raviprakash Rao, Texas Instruments, Inc.

3:10PM
5A.1
Post-Fabrication Calibration of Near-Threshold Circuits for Energy Efficiency
Mohammad Saber Golanbari¹, Saman Kiamehr², Fabian Oboril¹, Anteneh Gebregiorgis¹, Mehdi Tahoori^1
1Karlsruhe Institute of Technology, ²Karlsruhe Institute of Technology (KIT)

3:30PM
5A.2
Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing
Shaahin Angizi¹, Zhezhi He², Ronald F. DeMara³, Deliang Fan^3
1Department of Electrical and Computer Engineering, University of Central Florida, ²Department of ECE, University of Central Florida, ³University of Central Florida

3:50PM
5A.3
Low Latency Divider using Ensemble of Moving Average Curves
Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura
Hokkaido University

4:10PM
5A.4
Adder Implementation in Reconfigurable Resistive Switching Crossbar
Pravin Mane, Sudeep Mishra, Ravish Deliwala, Ramesha C. K.
BITS Pilani K K Birla Goa Campus

4:30PM
5A.5
High precision yet wide range on-chip oscillator with dual charge-discharge technique
Abhijit Das¹ and Joonsung Park^2
1Texas Instruments, ²Texas Instruments, Inc.

Chair: Srini Krishnamoorthy, Advanced Micro Devices Inc.
Co-Chair: Dae Hyun Kim, Washington State University

3:10PM
5B.1
In&Out: Restructuring for Threshold Logic Network Optimization
Chia-Chun Lin¹, Chiao-Wei Huang¹, Chun-Yao Wang¹, Yung-Chih Chen^2
1Department of Computer Science, National Tsing Hua University, ²Department of Computer Science & Engineering, Yuan Ze University

3:30PM
5B.2
Systematic Approximate Logic Optimization using Don't Care Conditions
Sahand Salamat¹, Mehrnaz Ahmadi¹, Bijan Alizadeh¹, Masahiro Fujita^2
1University of Tehran, ²University of Tokyo

3:50PM
5B.3
Comparative Study of Path Selection and Objective Function in Replacing NBTI Mitigation Logic
Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Kyoto University

4:10PM
5B.4
Methods for equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs
Qinhao Wang, Yusuke Kimura, Masahiro Fujita
University of Tokyo

4:30PM
5B.5
On Quality in Experimental Evaluation
Jan Schmidt
Czech Technical University in Prague

Chair: Vinod Viswanath, Real Intent
Co-Chair: Sreejit Chakravarty, Intel

3:10PM
5C.1
Cost-Quality Trade-offs of Approximate Memory Repair Mechanisms for Image Data
Qianqian Fan, Sachin Sapatnekar, David Lilja
University of Minnesota

3:30PM
5C.2
Aging-aware critical paths for process related validation in the presence of NBTI
phaninder alladi¹ and Spyros Tragoudas^2
1southern illinois university, ²Southern Illinois University Carbondale

3:50PM
5C.3
Broadcast Scan Compression Based on Deterministic Pattern Generation Algorithm
Hyeonchan Lim, Sungyoul Seo, Soyeon Kang, Sungho Kang
Yonsei University

4:10PM
5C.4
Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging
Jizhe Zhang¹ and Sandeep Gupta^2
1Electrical Engineering Department, University of Southern California, ²University of Southern California (USC)

4:30PM
5C.5
Failures and Verification Solutions Related to Untimed Paths in SOCs
Pranav Ashar¹, Vikas Sachdeva², Vinod Viswanath^2
1Real Intent, Inc, ²Real Intent, Inc.