ISQED 2017: Program
Rev. 4 (2/24/2017)


SESSION 1A

Tuesday March 14

Cognitive Computing on Conventional and Emerging Platforms

Chair: Yang Yi, University of Kansas
Co-Chair: Hai (Helen) Li, Duke University

10:25AM
1A.1
Electrical Modeling and Analysis of 3D Synaptic Array using Vertical RRAM Structure
Hongyu An1, M. Amimul Ehsan1, zhen zhou2, Yang Yi1
1University of Kansas, 2Intel Corporation

10:45AM
1A.2
SRAM Voltage Scaling for Energy-Efficient Convolutional Neural Networks
Lita Yang and Boris Murmann
Stanford University

11:05AM
1A.3
Stochastic-Based Multi-Stage Streaming Realization of Deep Convolutional Neural Network
Mohammed Alawad1 and Mingjie Lin2
1PhD student at UCF, 2University of Central Florida

11:25AM
1A.4
A Fast and Ultra Low Power Time-Based Spiking Neuromorphic Architecture for Embedded Applications
Tao Liu1 and Wujie Wen2
1ECE Department, Florida International University, 2Florida International University


SESSION 1B

Tuesday March 14

Design Opportunities and Challenges in Non-Volatile Technologies

Chair: Sumeet Kumar Gupta, Penn State University
Co-Chair: Jack Sampson, Penn State University

10:25AM
1B.1
Circuit Design for Beyond Von Neumann Applications Using Emerging Memory: From Nonvolatile Logics to Neuromorphic Computing
Meng-Fan (Marvin) Chang1, Wei-Hao Chen1, Win-San Khwa1, Jun-Yi Li1, Wei-Yu Lin1, Huan-Ting Lin1, Yongpan Liu2, Yu Wang2, Huaqiang Wu2, Huazhong Yang2
1National Tsing Hua University, 2Tsinghua University

10:45AM
1B.2
Harnessing Ferroelectrics for Non-volatile Memories and Logic
Sumeet Gupta1, Danni Wang2, Sumitha George2, Ahmedullah Aziz2, Xueqing Li2, Suman Datta3, Vijaykrishnan Narayanan2
1The Pennsylvania State University, 2Penn State University, 3University of Notre Dame

11:05AM
1B.3
Test Challenges in Embedded STT-MRAM Arrays
Insik Yoon and Arijit Raychowdhury
Georgia Institute of Technology

11:25AM
1B.4
Evaluating Tradeoffs in Granularity and Overheads in Supporting Nonvolatile Execution Semantics
Kaisheng Ma, Minli (Julie) Liao, Xueqing Li, Zhixuan Huan, John (Jack) Sampson
Penn State


SESSION 1C

Tuesday March 14

A Look into Future of Circuits, Interconnects and Memory with Emerging Technology

Chair: Jayita Das, INTEL
Co-Chair: Swatilekha Saha, Cypress Semiconductor Corporation

10:25AM
1C.1
Communication Limits of On-Chip Graphene Plasmonic Interconnects
Shaloo Rakheja
New York University

10:45AM
1C.2
Variation-Immune Resistive Non-Volatile Memory using Self-Organized Sub-Bank Circuit Designs
Navid Khoshavi, Soheil Salehi, Ronald F. DeMara
University of Central Florida

11:05AM
1C.3
Constructing Fast and Energy Efficient 1TnR based ReRAM Crossbar Memory
Lei Zhao1, Lei Jiang2, Youtao Zhang1, Nong Xiao3, Jun Yang1
1University of Pittsburgh, 2Indiana University Bloomington, 3National University of Defense Technology

11:25AM
1C.4
Learning to Trust an Emerging Technology: The Molecular Field Coupling Nanocomputing Case Study
Mariagrazia Graziano1, Ruiyu Wang1, Marco Vacca1, Fabrizio Riente1, Giovanna Turvani1, Franco Cacialli2, Gianluca Piccinini3
1Politecnico di Torino, 2University College London, 3Politecnico di Torino, University College London


SESSION 2A

Tuesday March 14

Low-Power/Fault-Tolerant Memories Using Scaled Technologies

Chair: Kurt Schwartz, Texas Instruments, Inc.
Co-Chair: Raviprakash Rao, Texas Instruments, Inc.

3:55PM
2A.1
Re-addressing SRAM Design and Measurement for Sub-threshold Operation in View of Classic 6T vs. Standard Cell Based Implementations
Xin Fan1, Jan Stuijt1, Rui Wang1, Bo Liu1, Tobias Gemmeke2
1Holst-Centre / imec, 2RWTH Aachen University

4:15PM
2A.2
Tunnel FET Based Ultra-Low-Leakage Compact 2T1C SRAM
Navneet Gupta1, Adam Makosiej2, Amara Amara3, Andrei Vladimirescu3, Costin Anghel4
1Institut supérieur d'électronique de Paris, France; LETI, Commissariat à l’Energie Atomique et aux Energies Alternatives (CEA-LETI) France;, 2LETI, Commissariat à l'énergie atomique et aux énergies alternatives (CEA-LETI) France, 3Institut supérieur d'électronique de Paris, 4ISEP

4:35PM
2A.3
Low Redundancy Matrix-Based codes for Adjacent Error Correction with Parity Sharing
Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao
Harbin Institute of Technology

4:55PM
2A.4
0.6 V operation, 16 % Faster Set/Reset ReRAM Boost Converter with Adaptive Buffer Voltage for ReRAM and NAND Flash Hybrid Solid-State Drives
Kota Tsurumi, Masahiro Tanaka, Ken Takeuchi
Chuo university


SESSION 2B

Tuesday March 14

Design for Manufacturability and Reliability

Chair: Vivek Joshi, GLOBALFOUNDRIES
Co-Chair: Jayita Das, INTEL

3:55PM
2B.1
Low Temperature Endurance Failures on Flash Memory
Steve Heinrich-Barna1, Clyde Dunn1, Douglas Verret2
1Texas Instruments, Inc, 2Texas Instruments, Inc (Retired)

4:15PM
2B.2
Virtual Characterization for Exhaustive DFM Evaluation of Logic Cell Libraries
Samuel Pagliarini, Mayler Martins, Lawrence Pileggi
Carnegie Mellon University

4:35PM
2B.3
Overview and development of EDA tools for integration of DSA into patterning solutions
Andres Torres, Germain Fenger, Daman Khaira, Yuansheng Ma, Yuri Granik, Chris Kapral, Joydeep Mitra, Polina Krasnova
Mentor Graphics Corporation

4:55PM
2B.4
Performance- and Energy-Aware Optimization of BEOL Interconnect Stack Geometry in Advanced Technology Nodes
Kwangsoo Han, Andrew Kahng, Hyein Lee, Lutong Wang
UCSD


SESSION P

Tuesday March 14

Posters

Chair: Steve Heinrich-Barna, Texas Instruments, Inc.
Co-Chair: Vinod Viswanath, Real Intent

5:15PM
P1
A Technique to Construct Global Routing Trees for Graphene Nanoribbon (GNR)
Subrata Das and Debesh Kumar Das
Jadavpur University

5:15PM
P2
Regularized Logistic Regression for Fast Importance Sampling Based SRAM Yield Analysis
Lama Shaer1, Rouwaida Kanj1, Rajiv Joshi2, Maria Malik3, Ali Chehab1
1American University of Beirut, 2IBM, 3George Mason University

5:15PM
P3
Binary Adder Circuit Design Using Emerging MIGFET Devices
Jeferson Baqueta, Felipe Marranghello, Augusto Neutzling, Vinicius Neves Possani, André Inacio Reis, Renato Perez Ribas
UFRGS

5:15PM
P4
A Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures
Sungkwan Ku1, Elliott Forbes2, Rangeen Basu Roy Chowdhury3, Eric Rotenberg4
1North Carolina State University, 2University of Wisconsin - La Crosse, 3Intel, 4North Carolina State University / Qualcomm

5:15PM
P5
Energy Efficient Analog Spiking Temporal Encoder with Verification and Recovery Scheme for Neuromorphic Computing Systems
Chenyuan Zhao, Jialing Li, Hongyu An, Yang Yi
University of Kansas

5:15PM
P6
3D-NOCET: A Tool for Implementing 3D-NoCs based on The Direct-Elevator Algorithm
maha Beheiry1, Hassan Mostafa2, Ahmed M. Soliman2
1Mentor Graphics, 2Cairo University

5:15PM
P7
Design Technology Co-Optimization of Back End of Line Design Rules for a 7 nm Predictive Process Design Kit
Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence Clark
Arizona State University

5:15PM
P8
Investigation of Magnetic Field Attacks on Commercial Magneto-Resistive Random Access Memory
Alexander Holst1, Jae-Won Jang2, Swaroop Ghosh2
1University of South Florida, 2Pennsylvania State University

5:15PM
P9
A 13T Radiation-Hardened Memory Cell for Low-Voltage Operation and Ultralow Power Space Applications
Chunhua Qi, Liyi Xiao, Mingxue Huo, Tianqi Wang, Rongsheng Zhang, Xuebing Cao
harbin institute of technology

5:15PM
P10
A New Approach for Selecting Inputs of Logic Functions During Debug
Amir Masoud Gharehbaghi1 and Masahiro Fujita2
1The University of Tokyo, 2University of Tokyo

5:15PM
P11
Fast and Energy-Aware Resource Provisioning and Task Scheduling for Cloud Systems
Hongjia Li1, Ji Li2, Wang Yao3, Shahin Nazarian2, Xue Lin4, Yanzhi Wang1
1Syracuse University, 2University of Southern California, 3High School in China, 4Northeastern University

5:15PM
P12
Evaluating the Benefits of a Relaxed BEOL Pitch for Deeply Scaled ICs
Mehmet M Isgenc, Samuel Pagliarini, Renzhi Liu, Larry Pileggi
Carnegie Mellon University

5:15PM
P13
STA Compatible Backend Design Flow for TSV-based 3-D ICs
Harry Kalargaris, Yi-Chung Chen, Vasilis Pavlidis
University of Manchester

5:15PM
P14
Off-Chip Test Architecture for Improving Multi-Site Testing Efficiency using Tri-State Decoder and 3V-Level Encoder
Sungyoul Seo1, Hyeonchan Lim1, Soyeon Kang1, Sungho Kang2
1Yonsei University, Seoul, Korea, 2Yonsei University

5:15PM
P15
Determining Proximal Geolocation of IoT Edge Devices via Covert Channel
Md Nazmul Islam, Vinay C Patil, Sandip Kundu
University of Massachusetts Amherst


SESSION 3A

Wednesday March 15

Power and Timing Optimization

Chair: Vinod Viswanath, Real Intent
Co-Chair: Anand Iyer, Microsoft

09:00AM
3A.1
Clock tree optimization through selective airgap insertion
Daijoon Hyun, Wachirawit Ponghiran, Youngsoo Shin
KAIST

09:20AM
3A.2
An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops
Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens
Eindhoven University of Technology

09:40AM
3A.3
High Sigma Statistical Hold Time Analysis in FinFET Sequential Circuits
Sam Lo, Taylor Lee, Aaron Barker
Oracle

10:00AM
3A.4
Power Prediction of Embedded Scalar and Vector Processor: Challenges and Solutions
Vijay Kiran Kalyanam1, Peter Sassone2, Jacob Abraham3
1Qualcomm Technologies, Inc., 2Qualcomm Technologies Inc., 3CERC, The University of Texas at Austin

10:20AM
3A.5
Power-Delay Product Based Resource Library Construction for Effective Power Optimization in HLS
Shantanu Dutt1 and Ouwen Shi2
1University of Illinois at Chicago, 2Univ. of Illinois at Chicago


SESSION 3B

Wednesday March 15

Hardware Security

Chair: Swaroop Ghosh, Penn State University
Co-Chair: Gang Qu, University of Maryland

09:00AM
3B.1
Crossover Ring Oscillator PUF
Zihan Pang1, Jiliang Zhang2, Qiang Zhou3, Shuqian Gong2, Xu Qian1, Bing Tang4
1China University of Mining & Technology (Beijing), 2Northeastern University, China, 3Tsinghua University, 4Guangdong Eshore Science and Technology Co., Ltd

09:20AM
3B.2
Integrated Circuit Identification and True Random Numbers using 1.5-Transistor Flash Memory
Lawrence Clark, James Adams, Keith Holbert
Arizona State University

09:40AM
3B.3
Methodologies to Exploit ATPG Tools for De-camouflaging
Deepakreddy* Vontela1 and Swaroop Ghosh2
1University of South florida, 2Pennsylvania State University

10:00AM
3B.4
Low-Overhead Implementation of Logic Encryption Using Gate Replacement Techniques
Xiaoming Chen1, Qiaoyi Liu1, Yu Wang1, Qiang Xu2, Huazhong Yang1
1Tsinghua University, 2The Chinese University of Hong Kong

10:20AM
3B.5
Scan Chain based IP Fingerprint and Identification
Xi Chen1, Gang Qu1, Aijiao Cui2, Carson Dunbar1
1University of Maryland, 2Harbin Institute of Technology Shenzhen Graduate School


SESSION 3C

Wednesday March 15

Novel Reliability Solutions for 3D ICs

Chair: Payman Zarkesh-Ha, University of New Mexico
Co-Chair: Vivek Joshi, GLOBALFOUNDRIES

09:00AM
3C.1
Performance-Thermal Trade-offs for a VFI-Enabled 3D NoC Architecture
Dongjin Lee, Sourav Das, Partha Pande
Washington State University

09:20AM
3C.2
A Legalization Algorithm for Multi-Tier Gate-Level Monolithic Three-Dimensional Integrated Circuits
Yiting Chen and Dae Hyun Kim
Washington State University

09:40AM
3C.3
Cooling Architectures using Thermal Sidewalls, Interchip Plates, and Bottom Plate for 3D ICs
Kaoru Furumi, Masashi Imai, Atsushi Kurokawa
Hirosaki University

10:00AM
3C.4
High Performance Virtual Channel Based Fully Adaptive Thermal-aware Routing for 3D NoC
Xin Jiang, Xiangyang Lei, Lian Zeng, Takahiro Watanabe
Graduate School of Information, Production & Systems, Waseda University

10:20AM
3C.5
Data Interface Buffer Compensation Scheme for Fast Calibration
Sameer Shekhar, Amit Kumar Jain, Pooja Nukala
Intel Corporation


SESSION 4A

Wednesday March 15

Lightweight Security for Internet-of-Things: Attacks, Countermeasures and Efficient Implementations

Chair: Shivam Bhasin, Nanyang Tech. University
Co-Chair: Anupam Chattopadhyay, Nanyang Tech. University

10:50AM
4A.1
Chosen-Input Side-Channel Analysis on Unrolled Light-Weight Cryptographic Hardware
Ville Yli-Mäyry, Naofumi Homma, Takafumi Aoki
Tohoku University

11:10AM
4A.2
An Electromagnetic Fault Injection Sensor using Hogge Phase-Detector
Wei He, Jakub Breier, Shivam Bhasin
Nanyang Technological University

11:30AM
4A.3
FPGA Implementation of Modeling Attack Resistant Arbiter PUF with Enhanced Reliability
Siarhei S. Zalivaka1, Alexander A. Ivaniuk2, Chip Hong Chang1
1Nanyang Technological University, 2Belarusian State University of Informatics and Radioelectronics

11:50AM
4A.4
Towards Lightweight Identity-Based Encryption for the Post-Quantum-Secure Internet of Things
Tim Güneysu1 and Tobias Oder2
1University of Bremen & DFKI, 2Ruhr-Universität Bochum

12:10PM
4A.5
SHA-3 Implementation Using ReRAM based In-Memory Computing Architecture
Debjyoti Bhattacharjee, Vikramkumar Pudi, Anupam Chattopadhyay
Nanyang Technological University


SESSION 4B

Wednesday March 15

Design for Smart Sensors and Internet of Things

Chair: Libor Rufer, University Grenoble-Alpes, France
Co-Chair: Kamesh Gadepally, GigaCom Semiconductor

10:50AM
4B.1
A Hybrid RFID and CV System for Item-Level Localization of Stationary Objects
Everton Berz, Deivid Tesch, Fabiano Hessel
PUCRS University

11:10AM
4B.2
Energy Efficient Biopotential Acquisition Unit for Wearable Health Monitoring Applications
Wazir Singh, Yatharth Gupta, Paritosh Jivani, Sujay Deb
IIIT Delhi

11:30AM
4B.3
Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice
Leo Filippini1, Diane Lim2, Lunal Khuon1, Baris Taskin1
1Drexel University, 2University of Pennsylvania

11:50AM
4B.4
CAP: Configurable Resistive Associative Processor for Near-Data Computing
Mohsen Imani1 and Tajana Rosing2
1University of California San Diego, 2UCSD

12:10PM
4B.5
Low-power MEMS-based sensors
David Horsley
University of California, Davis


SESSION 4C

Wednesday March 15

Innovative Energy Management for Modern Systems

Chair: Vivek Nandakumar, Cadence Design Systems
Co-Chair: Steve Heinrich-Barna, Texas Instruments, Inc.

10:50AM
4C.1
Performance Evaluation of Copper and Graphene Nanoribbons in 2-D NoC Structures.
Ruturaj Pujari and Shaloo Rakheja
New York University

11:10AM
4C.2
Processor/Memory Co-scheduling Using Periodic Resource Server for Real-Time System Under Peak Temperature Constraints
Gustavo A. Chaparro-Baquero, Shi Sha, Soamar Homsi, Wujie Wen, Gang Quan
Florida International University

11:30AM
4C.3
Data Center Power Management for Regulation Service Using Neural Network-Based Power Prediction
Ning Liu1, Xue Lin2, Yanzhi Wang1
1Syracuse University, 2Northeastern University

11:50AM
4C.4
An Energy Efficient Non-uniform Last Level Cache Architecture in 3D Chip-Multiprocessors
pooneh safayenikoo1, Arghavan Asad2, Mahmood Fathy2, Farah Mohammadi3
1School of Computer Engineering, iran university of science and technology, 2Iran University of Science and Technology, 3Ryerson University

12:10PM
4C.5
Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors
Scott Lerner and Baris Taskin
Drexel University


SESSION 5A

Wednesday March 15

Energy Efficient Logic Design Using Scaled Technologies

Chair: Kurt Schwartz, Texas Instruments, Inc.
Co-Chair: Raviprakash Rao, Texas Instruments, Inc.

3:10PM
5A.1
Post-Fabrication Calibration of Near-Threshold Circuits for Energy Efficiency
Mohammad Saber Golanbari1, Saman Kiamehr2, Fabian Oboril1, Anteneh Gebregiorgis1, Mehdi Tahoori1
1Karlsruhe Institute of Technology, 2Karlsruhe Institute of Technology (KIT)

3:30PM
5A.2
Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing
Shaahin Angizi1, Zhezhi He2, Ronald F. DeMara3, Deliang Fan3
1Department of Electrical and Computer Engineering, University of Central Florida, 2Department of ECE, University of Central Florida, 3University of Central Florida

3:50PM
5A.3
Low Latency Divider using Ensemble of Moving Average Curves
Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura
Hokkaido University

4:10PM
5A.4
Adder Implementation in Reconfigurable Resistive Switching Crossbar
Pravin Mane, Sudeep Mishra, Ravish Deliwala, Ramesha C. K.
BITS Pilani K K Birla Goa Campus

4:30PM
5A.5
High precision yet wide range on-chip oscillator with dual charge-discharge technique
Abhijit Das1 and Joonsung Park2
1Texas Instruments, 2Texas Instruments, Inc.


SESSION 5B

Wednesday March 15

Synthesis and Reliability

Chair: Srini Krishnamoorthy, Advanced Micro Devices Inc.
Co-Chair: Dae Hyun Kim, Washington State University

3:10PM
5B.1
In&Out: Restructuring for Threshold Logic Network Optimization
Chia-Chun Lin1, Chiao-Wei Huang1, Chun-Yao Wang1, Yung-Chih Chen2
1Department of Computer Science, National Tsing Hua University, 2Department of Computer Science & Engineering, Yuan Ze University

3:30PM
5B.2
Systematic Approximate Logic Optimization using Don't Care Conditions
Sahand Salamat1, Mehrnaz Ahmadi1, Bijan Alizadeh1, Masahiro Fujita2
1University of Tehran, 2University of Tokyo

3:50PM
5B.3
Comparative Study of Path Selection and Objective Function in Replacing NBTI Mitigation Logic
Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Kyoto University

4:10PM
5B.4
Methods for equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs
Qinhao Wang, Yusuke Kimura, Masahiro Fujita
University of Tokyo

4:30PM
5B.5
On Quality in Experimental Evaluation
Jan Schmidt
Czech Technical University in Prague


SESSION 5C

Wednesday March 15

Verification and Test

Chair: Vinod Viswanath, Real Intent
Co-Chair: Sreejit Chakravarty, Intel

3:10PM
5C.1
Cost-Quality Trade-offs of Approximate Memory Repair Mechanisms for Image Data
Qianqian Fan, Sachin Sapatnekar, David Lilja
University of Minnesota

3:30PM
5C.2
Aging-aware critical paths for process related validation in the presence of NBTI
phaninder alladi1 and Spyros Tragoudas2
1southern illinois university, 2Southern Illinois University Carbondale

3:50PM
5C.3
Broadcast Scan Compression Based on Deterministic Pattern Generation Algorithm
Hyeonchan Lim, Sungyoul Seo, Soyeon Kang, Sungho Kang
Yonsei University

4:10PM
5C.4
Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging
Jizhe Zhang1 and Sandeep Gupta2
1Electrical Engineering Department, University of Southern California, 2University of Southern California (USC)

4:30PM
5C.5
Failures and Verification Solutions Related to Untimed Paths in SOCs
Pranav Ashar1, Vikas Sachdeva2, Vinod Viswanath2
1Real Intent, Inc, 2Real Intent, Inc.