Accurate timing characterization of flip-flops is critical for robust circuit design. Conventionally, setup time and hold time are characterized independently, which results in pes- simistic/optimistic designs. To reduce this pessimism/optimism, the interdependency between setup/hold-time has to be taken into account. Fast and accurate characterization of the setup/hold- time interdependency is however a challenging task. In this paper, an analytical model is proposed to capture the setup/hold- time interdependency in a conventional master-slave flip-flop. The accuracy of the proposed model is ∼10X higher than the previously published characterization methods. Furthermore, a flow is proposed to find the parameters of the model with ∼2.5X shorter computation time compared to the existing methods.