Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a emerging memory technology which exhibits non-volatility, high density and nanosecond read and write times. These attributes of STT-MRAM make it suitable for last level embedded caches. However, the defects and corresponding fault models of STT-MRAM are not as extensively explored as in SRAM and therefore, there is a growing need for defect and fault analysis. Moreover, stochastic retention failure of STTMRAM imposes a large burden in testing time. Conventional test schemes for retention of STT-MRAM need to be optimized for testing large-size embedded STT-MRAM array. This work presents an review of the different defect and fault mechanisms as well as a BIST architecture and circuit to reduce testing time in characterization and manufacturing tests for retention. We address the effect magnetic coupling between cells on retention of the cells and identify test setup for worst case retention.