In Deep sub-micron design level, interconnect plays an important role in VLSI circuit designs. Traditional interconnects are facing several challenges such as delay and power dissipation. {\em Graphene nanoribbons (GNRs)} have been found to be potential alternative for both transistors and interconnects due to its outstanding electrical and thermal properties. The construction of minimum cost global routing trees is a key challenge in deep sub-micron design. The construction of such trees for traditional interconnects based on {\em Required Arrival Times (RAT)} has been reported in literature. Construction of global routing trees for {\em GNR} routing are different than that of traditional interconnects. In this paper, we propose an algorithm for the construction of cost effective global routing trees for {\em GNR} routing based on {\em required arrival time}. We formulate the {\em GNR} routing problem considering the minimization of the area of triangular grid such that delay from source to each of the sink terminals is within given time budget. The algorithm is tested on a random set of data and the results obtained are quite encouraging.