While pausing and resuming execution using nonvolatile storage has long been possible, nonvolatile processing as a fundamental paradigm has only recently been made practical by technology advances allowing on-chip nonvolatile memories. However, even with on-chip nonvolatile storage, the granularity of ensured forward progress that a nonvolatile processor offers can still vary widely from cycle-level guarantees to software-defined checkpoints spanning potentially significant quantities of execution. Choice of supported granularity influences not only the hardware overheads, but also the complexity of avoiding potential inconsistencies between architectural and microarchitectural state in realistic memory systems. In this paper, we examine the overheads, in terms of both complexity and efficiency, for non-volatile processor designs with different granularities of forward progress guarantees.