Tunnel FET Based Ultra-Low-Leakage Compact 2T1C SRAM

Navneet Gupta1, Adam Makosiej2, Amara Amara3, Andrei Vladimirescu3, Costin Anghel4
1Institut supérieur d'électronique de Paris, France; LETI, Commissariat à l’Energie Atomique et aux Energies Alternatives (CEA-LETI) France;, 2LETI, Commissariat à l'énergie atomique et aux énergies alternatives (CEA-LETI) France, 3Institut supérieur d'électronique de Paris, 4ISEP

Abstract

In this paper, ultra-low-leakage 2T1C compact SRAM is proposed using Tunnel FETs (TFETs). Proposed design utilizes negative differential resistance property of TFETs and capacitor leakage to implement 1T1C latch. Additional 1T read port is added for reading to avoid data stability issues during read operation. Proposed SRAM design is scalable and easily adaptable for lower technology nodes. Ultra-low leakage below 1fA/bit is achieved in the proposed design. Read and write cycle times of sub-2ns and sub-4ns are designed.