Chair: Stephen Heinrich-Barna, Texas Instruments
Co-Chair: Saibal Mukhopadhyay, Georgia Tech

10:20AM
1A.1
A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs
Arijit Banerjee¹,  Mahmut E. Sinangil²,  John Poulton²,  C. Thomas Gray²,  Benton H. Calhoun^1
1University of Virginia, ²NVIDIA

10:40AM
1A.2
Exploiting Static and Dynamic Locality of Timing Errors in Robust L1 Cache Design
Hu Chen,  Sanghamitra Roy,  Koushik Chakraborty
Utah State University

11:00AM
1A.3
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering ×91 Failure Rate Improvement
Yohei Nakata¹,  Yuta Kimi¹,  Shunsuke Okumura¹,  Jinwook Jung¹,  Takuya Sawada¹,  Taku Toshikawa¹,  Makoto Nagata²,  Hirofumi Nakano³,  Makoto Yabuuchi³,  Hidehiro Fujiwara³,  Koji Nii³,  Hiroyuki Kawai³,  Hiroshi Kawaguchi¹,  Masahiko Yoshimoto^2
1Kobe University, ²Kobe University, JST CREST, ³Renesas Electronics Corporation

11:20AM
1A.4
40nm ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU
Yoshisato Yokoyama,  Yuichiro Ishii,  Hidemitsu Kojima,  Atsushi Miyanishi,  Yoshiki Tsujihashi,  Shinobu Asayama,  Kazutoshi Shiba,  Koji Tanaka,  Tatsuya Fukuda,  Koji Nii,  Kazumasa Yanagisawa
Renesas Electronics Corporation

11:40AM
1A.5
Impact of Proactive Reconfiguration Technique on Vmin and Lifetime of SRAM Caches
Peyman Pouyan,  Esteva Amat,  Enrique Barajas,  Antonio Rubio
Department of Electronic Engineering UPC Barcelona Tech

Chair: James Lei, Omnivision

10:20AM
1B.1
Modeling, Design and Verification Platform using SystemC AMS
Yao Li,  Ramy Iskander,  Marie-Minerve Louërat
UPMC-LIP6

10:40AM
1B.2
On Application of One-class SVM to Reverse Engineering-Based Hardware Trojan Detection
Chongxi Bao¹,  Domenic Forte²,  Ankur Srivastava^1
1University of Maryland, ²University of Connecticut

11:00AM
1B.3
Employing a Timed Colored Petri Net to Achieve an Accurate Model for NoC Performance Evaluation
César Marcon¹,  Jarbas Silveira²,  Paulo Cortez²,  Giovani Barroso^3
1PPGCC / PUCRS, ²LESC-DETI / UFC, ³UFC

11:20AM
1B.4
Integrated Particle Swarm Optimization (i-PSO): An Adaptive Design Space Exploration Framework for Power-Performance Tradeoff in Architectural Synthesis
Anirban Sengupta and Vipul Kumar Mishra
Indian Institute of Technology - IIT Indore

11:40AM
1B.5
Modeling and Analysis of System Stability in a Distributed Power Delivery Network with Embedded Digital Linear Regulators
Saad Bin Nasir,  Youngtak Lee,  Arijit Raychowdhury
Georgia Institute of Technology

Chair: Rajesh Berigei, Texas Instruments
Co-Chair: Jose Matos, University of Porto, Portugal

10:20AM
1C.1
An Application-Aware Heterogeneous Prioritization Framework for NoC-based Chip Multiprocessors
Tejasi Pimpalkhute and Sudeep Pasricha
Colorado State University

10:40AM
1C.2
Adding virtualization support in MIPS 4Kc-based MPSoCs
Alexandra Aguiar,  Carlos Moratelli,  Marcos Sartori,  Fabiano Hessel
PUCRS

11:00AM
1C.3
HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific Network-On-Chip Architectures
Shirish Bahirat and Sudeep Pasricha
Department of Electrical and Computer Engineering Colorado State University

11:20AM
1C.4
An Analytical Approach to System-level Variation Analysis and Optimization for Multi-core Processors
Chenyun Pan,  Saibal Mukhopadhyay,  Azad Naeemi
Georgia Institute of Technology

11:40AM
1C.5
Heterogeneity Exploration for Peak Temperature Reduction on Multi-Core Platforms
Tianyi Wang¹,  Ming Fan¹,  Gang Quan¹,  Shangping Ren^2
1Florida International University, ²Illinois Institute of Technology

Chair: Sreejit Chakravarty, LSI Corporation
Co-Chair: Senthil Arasu, Broadcom

1:30PM
2A.1
Efficient Post-Silicon Validation via Segmentation of Process Variation Envelope – Global vs Local Variations
Prasanjeet Das¹ and Sandeep Gupta^2
1Oracle America Inc., ²University of Southern California

1:50PM
2A.2
Protection of Muller-Pipelines from Transient Faults
Syed Rameez Naqvi,  Jakob Lechner,  Andreas Steininger
Vienna University of Technology

2:10PM
2A.3
Runtime Fault Recovery Protocol for NoC-based MPSoCs
eduardo wachter,  augusto erichsen,  leonardo juracy,  alexandre amory,  fernando moraes
PUCRS

2:30PM
2A.4
Concurrency-Oriented SoC Re-Certification by Reusing Block-Level Test Vectors
Hsuan-Ming Chou,  Hong-Chang Wu,  Yi-Chiao Chen,  Shih-Chieh Chang
National Tsing Hua University

2:50PM
2A.5
Efficient Trace Signal Selection using Augmentation and ILP Techniques
Kamran Rahmani¹,  Prabhat Mishra¹,  Sandip Ray^2
1University of Florida, ²Intel Corporation

3:10PM
2A.6
Directed Test Generation for Hybrid Systems
Sudhi Proch and Prabhat Mishra
University Of Florida

Chair: Farhang Yazdani, Broadpak
Co-Chair: Srinivas Bodapati, Intel

1:30PM
2B.1
Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache
Kyungsu Kang¹,  Seunghan Lee²,  Giovanni De Micheli³,  Chong-Min Kyung^2
1Samsung, ²KAIST, ³EPFL

1:50PM
2B.2
Efficient Region-Aware P/G TSV Plannng for 3D ICs
Song Yao¹,  Xiaoming Chen¹,  Yu Wang¹,  Yuchun Ma²,  Yuan Xie³,  Huazhong Yang^1
1Dept. of E.E., TNList, Tsinghua Univ., China, ²Dept. of C.S., TNList, Tsinghua Univ., China, ³Computer Science and Engr. Dept, Pennsylvania State University, U.S.A.

2:10PM
2B.3
3D-ICs with Self-Healing Capability for Thermal Effects in RF Circuits
Abhilash Goyal¹,  Madhavan Swaminathan²,  Abhijit Chatterjee^2
1IEEE Member Student at San Jose State, ²Professor at GaTech

2:30PM
2B.4
Comparative Analysis of Clock Distribution Networks for TSV-based 3D IC Designs
Mir mohammad Navidi and Gyung-Su Byun
West Virginia University

2:50PM
2B.5
Delay and Power Optimization with TSV-aware 3D Floorplanning
Mohammad Ahmed and Malgorzata Chrzanowska-Jeske
Portland State University

3:10PM
2B.6
Runtime 3-D Stacked Cache Data Management for Energy Minimization of 3-D Chip-Multiprocessors
Seunghan Lee¹,  Kyungsu Kang²,  Jongpil Jung¹,  Chong-Min Kyung^1
1EE, Korea Advanced Institute of Science and Technology, Daejeon, Korea, ²LSI, EPFL, Lausanne, Switzerland

Chair: Brian Cline, ARM
Co-Chair: Srini Krishnamoorthy, AMD

1:30PM
2C.1
Statistical Methodology for Modeling Non-IID Memory Fails Events
Sabine Francis¹,  Rouwaida Kanj¹,  Rajiv Joshi²,  Ayman Kayssi¹,  Ali Chehab^1
1American University of Beirut, ²IBM TJ Watson Labs

1:50PM
2C.2
Automated Shmoo Data Analysis: A Machine Learning Approach
Wei Wang
Intel Corporation

2:10PM
2C.3
Double Patterning-Aware Detailed Routing with Mask Usage Balancing
Seong-I Lei¹,  Chris Chu²,  Wai-Kei Mak^1
1National Tsing Hua University, ²Iowa State University

2:30PM
2C.4
Design of Radiation Hardened Wide Tuning Range CMOS Oscillators
Sharayu Jagtap,  Sivaramakrishna R,  Shalabh Gupta
Indian Institute of Technoloogy Bombay

2:50PM
2C.5
Computer Simulation of Radiation-Induced Clock-Perturbation in Phase-Locked Loop with Analog Behavioral Model
Tomohiro FUJITA¹,  SinNyoung KIM²,  Hidetoshi ONODERA^2
1Ritsumeikan University, ²Kyoto University

3:10PM
2C.6
Measuring SET Pulsewidths in Logic Gates using Digital Infrastructure
Varadan Savulimedu Veeravalli,  Andreas Steininger,  Ulrich Schmid
Vienna University of Technology

Chair: Visvesh Sathe, Univerity of Washington Seatle
Co-Chair: Saibal Mukhopadhyay, Georgia Tech

3:50PM
3A.1
Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits
Yanqing Zhang and Benton Calhoun
University of Virginia

4:10PM
3A.2
An Improved Logical Effort Model and Framework Applied to Optimal Sizing of Circuits Operating in Multiple Supply Voltage Regimes
Xue Lin,  Yanzhi Wang,  Shahin Nazarian,  Massoud Pedram
University of Southern California

4:30PM
3A.3
Sub-threshold Custom Standard Cell Library Validation
Bo Liu¹,  Maryam Ashouei²,  Tobias Gemmeke²,  Jose Pineda de Gyvez^1
1Electronic Systems, Electrical Engineering, Technische Univ. Eindhoven, Eindhoven, NL, ²Holst Centre/imec-nl, Eindhoven, NL

4:50PM
3A.4
Power and Area-Efficient Approximate Wallace Tree Multiplier for Error-Resilient Systems
Kartikeya Bhardwaj¹,  Pravin Mane²,  Joerg Henkel^3
1Electrical & Electronics Engineering, BITS Pilani-Goa Campus, Goa-403726, India, ²Electrical & Electronics Engineering, BITS Pilani – Goa Campus Goa -403726 India, ³Department of Computer Science, Karlsruhe Institute of Technology, Karlsruhe, Germany

5:10PM
3A.5
Predictive Synchronization for DVFS-Enabled Multi-Processor Systems
Mark Buckler and Wayne Burleson
UMass Amherst, AMD Research

Chair: Sudeep Pasricha, Colorado State Univ
Co-Chair: Houman Homayoun, George Mason University

3:50PM
3B.1
Ring-based Sharing Fabric for Efficient Pipelining of Kernel-Stream on CGRA-based Multi-Core Architecture
Heesun Kim,  Seungyun Sohn,  Yoonjin Kim
Department of Computer Science, Sookmyung Women’s University

4:10PM
3B.2
Multi-Core Partitioned Scheduling For Fixed-Priority Periodic Real-Time Tasks With Enhanced RBound
Ming Fan¹,  Qiushi Han²,  Gang Quan¹,  Shangping Ren^3
1Florida International University, ²Florida International Unversity, ³Illinois Institute of Technology

4:30PM
3B.3
Minimizing Clock Domain Crossing in Network on Chip Interconnect
Parag Kulkarni¹,  Puneet Gupta²,  Rudy Beraha^3
1Synopsys, ²UCLA, ³Qualcomm

4:50PM
3B.4
Optimal Reliability-Constrained Overdrive Frequency Selection In Multicore Systems
Andrew B. Kahng and Siddhartha Nath
University of California, San Diego

5:10PM
3B.5
RTL Datapath Optimization Using System-level Transformations
Samaneh Ghandali¹,  Bijan Alizadeh¹,  Masahiro Fujita²,  Zainalabedin Navabi^1
1School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran, ²VLSI Design and Education Center (VDEC), University of Tokyo, Tokyo, Japan

Chair: Paul Tong, Pericom
Co-Chair: Bao Liu, University of Texas, San Antonio

3:50PM
3C.1
Dual-sided Doped Memristor and Its SPICE Modeling for Improved Electrical Properties
Anup Shrivastava¹ and Jawar Singh^2
1IIITDM, Jabalpur, ²IIITDM,Jabalpur

4:10PM
3C.2
Linearly Separable Pattern Classification Using Memristive Crossbar Circuits
Komal Singh,  Chitrakant Sahu,  Jawar Singh
Indian Institute of Information Technology Design and Manufacturing, Jabalpur, India

4:30PM
3C.3
Low-power programmable-logic array using nonvolatile complementary atom switch
Makoto Miyamura,  Toshitsugu Sakamoto,  Munehiro Tada,  Naoki Banno,  Koichi Okamoto,  Noriyuki Iguchi,  Hiromitsu Hada
LEAP

4:50PM
3C.4
Volume Accumulated Double Gate Junctionless MOSFETs for Low Power Logic Technology Applications
Mukta Singh Parihar and Abhinav Kranti
Indian Institute of Technology Indore (IITI), India

5:10PM
3C.5
Stack Sizing Analysis and Optimization for FinFET Logic Cells and Circuits Operating in the Sub/Near-Threshold Regime
Xue Lin,  Yanzhi Wang,  Massoud Pedram
University of Southern California

Chair: Peter Wright, Synopsys
Co-Chair: Syed M Alam, Everspin Technologies

5:30PM
P.1
A Parallel Clustering Algorithm for Placement
Amir Momeni,  Perhaad Mistry,  David Kaeli
Department of Electrical and Computer Engineering, Northeastern University

5:30PM
P.2
An Optimization Algorithm for Simultaneous Routing and Buffer Insertion with Delay-Power Constraints in VLSI Layout Design
Chessda Uttraphan¹,  Nasir Shaikh-Husin²,  Mohamed Khalil-Hani^2
1Universiti Tun Hussein Onn Malaysia (UTHM), ²Universiti Teknologi Malaysia (UTM)

5:30PM
P.3
Kriging Bootstrapped Neural Network Training for Fast and Accurate Process Variation Analysis
Oghenekarho Okobiah,  Saraju Mohanty,  Elias Kougianos
University of North Texas, Denton

5:30PM
P.4
Design and Analysis of a Touch Mode MEMS Capacitive Pressure Sensor for IUPC
Anil sharma and Jawar Singh
IIITDM Jabalpur

5:30PM
P.5
Impedance Modeling of Intracortical Microelectrode for a Reliable Design of Brain Activity Recording System
Daniela De Venuto¹,  Peter Ledochowitsch²,  Michel Maharabitz²,  Jan Rabaey^2
1Politecnico di Bari, Italy, ²UC Berkeley (CA) USA

5:30PM
P.6
Direct Finite-Element-Based Solver for 3D-IC Thermal Analysis via H-Matrix Representation
Ying Chi Li¹,  Sheldon X.-D. Tan²,  Tan Yu²,  Xin Huang²,  Ngai Wong^1
1The University of Hong Kong, ²University of California, Riverside

5:30PM
P.7
Compiler-Directed Leakage Energy Reduction for Instruction Scratch-Pad Memories
Yijie Huangfu and Wei Zhang
Virginia Commonwealth University

5:30PM
P.8
Fast Design Space Subsetting for Configurable Caches
Mohamad Hammam Alsafrjalani¹,  Ann Gordon-Ross¹,  Pablo Viana^2
1University of Florida, ²Federal University of Alagoas, FEAC dept., Brazil

5:30PM
P.9
A Framework for MPSoC Generation and Distributed Applications Evaluation
Guilherme Machado de Castilhos,  Eduardo Weber Wachter,  Guilherme Afonso Madalozzo,  Augusto Gosmann Erichsen,  Thiago Mânica Monteiro,  Fernando Gehm Moraes
PUCRS

5:30PM
P.10
Architecture for Monitoring SET Propagation in 16-bit Sklansky Adder
Varadan Savulimedu Veeravalli and Andreas Steininger
Vienna University of Technology, Austria

5:30PM
P.11
Towards more Reliable Embedded Systems through a Mechanism for Monitoring Driver Devices Communication
Rafael Melo Macieira,  Edna Barros,  Camila Ascendina
CIn/UFPE

5:30PM
P.12
Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits
Takashi Sato¹,  Junya Kawashima¹,  Hiroshi Tsutsui²,  Hiroyuki Ochi^3
1Kyoto University, ²Hokkaido University, ³Ritsumeikan University

5:30PM
P.13
Application of Six-Sigma DMAIC Methodology in the Evaluation of Test Effectiveness: A Case Study for EDA Tools
Eman El Mandouh
Quality Assurance Manager for Questa Formal Tools

5:30PM
P.14
Systematic Analyses for Latching Probability of Single-Event Transients
Hoda Pahlevanzadeh and Qiaoyan Yu
University of New Hampshire

5:30PM
P.15
GPU-Accelerated Sparse Matrix-Vector Multiplication For Fast Transient Thermal Analysis
Kai He¹,  Tan Yu¹,  Sheldon Tan¹,  Hai Wang²,  He Tang^2
1University of California, Riverside, ²UESTC

Chair: Rajiv Joshi, IBM
Co-Chair: Arijit Raychowdhury, Georgia Tech

10:20AM
4A.1
Assessment of Reliability Impact on GHz Processors with Moderate Overdrive
Mitsuhiko Igarashi,  Hideki Aono,  Hideaki Abe,  Koji Shibutani,  Kan Takeuchi
Renesas Electronics Corporation

10:40AM
4A.2
Study of IC Aging on Ring Oscillator Physical Unclonable Functions
Dinesh Ganta and Leyla Nazhandali
Virginia Tech

11:00AM
4A.3
Circuit-level approach to improve the temperature reliability of Bi-stable PUFs
Dinesh Ganta and Leyla Nazhandali
Virginia Tech

11:20AM
4A.4
Degradation Analysis of Datapath Logic Subblocks under NBTI Aging in FinFET Technology
Halil Kukner¹,  Moustafa Khatib²,  Sebastien Morrison²,  Pieter Weckx¹,  Praveen Raghavan²,  Ben Kaczer²,  Francky Catthoor¹,  Liesbet Van der Perre¹,  Rudy Lauwereins¹,  Guido Groeseneken^1
1imec,KUL, ²imec

11:40AM
4A.5
Fine Grained Wearout Sensing using Metastability Resolution Time
Vikram Suresh and Wayne Burleson
University of Massachusetts, Amherst

Chair: Vamsi Srikantam, Veloce Technologies

10:20AM
4B.1
Methodology to Optimize Critical Node Seperation in Hardened Flip-Flops
Sandeep Shambhulingaiah,  Srivatsan Chellappa,  Sushil Kumar,  Lawrence Clark
Arizona State University

10:40AM
4B.2
Asymmetric Aging of Clock Networks in Power Efficient Designs
Senthil Arasu¹,  Mehrdad Nourani¹,  Frank Cano²,  John Carulli²,  Vijay Reddy^2
1University of Texas at Dallas, ²Texas Instruments Inc

11:00AM
4B.3
Post-Silicon Tunable Clock Buffer Allocation Based on Fast Chip Yield Computation
Hyungjung Seo¹ and Taewhan Kim^2
1School of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea, ²Nano Systems Institute (NSI), Seoul National University, Seoul, Korea

11:20AM
4B.4
Timing Margin Recovery With Flexible Flip-Flop Timing Model
Andrew B. Kahng and Hyein Lee
UC San Diego

11:40AM
4B.5
NOLO : A No-Loop, Predictive Useful Skew Methodology for Improved Timing in IC Implementation
Tuck-Boon Chan,  Andrew B. Kahng,  Jiajia Li
UCSD

Chair: Miroslav Velev, Aries Design Automation
Co-Chair: Anand Iyer, AMD

10:20AM
4C.1
Constructing Small-Signal Equivalent Impedances Using Ellipsoidal Norms
Sandeep Koranne
Mentor Graphics Corporation

10:40AM
4C.2
Sense Amplifier Pass Transistor Logic For Energy Efficient and DPA-Resistant AES Circuit
Mehrdad Khatir and leyla Nazhandali
Virginia Tech

11:00AM
4C.3
Assessing Uniqueness and Reliability of SRAM-based Physical Unclonable Functions from Silicon Measurements in 45-nm bulk CMOS
Hidehiro Fujiwara,  Makoto Yabuuchi,  Koji Nii
Renesas Electronics Corporation

11:20AM
4C.4
TASSER: A Temperature-Aware Statistical Soft-Error-Rate Analysis Framework for Combinational Circuits
Sung S.-Y. Hsueh,  Ryan H.-M. Huang,  Charles H.-P. Wen
Department of Electrical and Computer Engineering, National Chiao Tung University

11:40AM
4C.5
PETS: Power and Energy Estimation Tool at System-Level
Santhosh Kumar Rethinagiri¹,  Oscar Palomar²,  Rabie Ben Atitallah³,  Adrian Cristal²,  Osman Unsal²,  Smail Niar^3
1BSC-Microsoft Research Center, ²Barcelona Supercomputing Center, ³University of Valenciennes

Chair: Paul Tong, Pericom
Co-Chair: Bao Liu, University of Texas, San Antonio

1:30PM
5A.1
Impact of FinFET Technology for Power Gating in Nano-Scale Design
Keunwoo Kim¹,  Rouwaida Kanj²,  Rajiv Joshi^3
1Samsung, ²American University of Beirut, ³IBM TJ Watson

1:50PM
5A.2
Avoiding Unnecessary Write Operations in STT-MRAM for Low Power Implementation
Rajendra Bishnoi,  Fabian Oboril,  Mojtaba Ebrahimi,  Mehdi Tahoori
Karlsruhe Institue of Technology

2:10PM
5A.3
A Workload-Aware-Design of 3D-NAND Flash Memory for Enterprise SSDs
Chao Sun¹,  Ayumi Soga²,  Takahiro Onagi²,  Koh Johguchi²,  Ken Takeuchi^2
1Chuo Univ./Univ. of Tokyo, ²Chuo Univ.

2:30PM
5A.4
A Compact Realization of a Quantum n-Bit Square Root Circuit
Nusrat Jahan lisa¹ and Hafiz Md. Hasan Babu^2
1Ahsanullah University of Science and Technology, Dhaka, Bangladesh, ²University of Dhaka, Bangladesh

2:50PM
5A.5
Statistical Process Variation Analysis of a Graphene FET based LC-VCO for WLAN Applications
Abir Khan,  Saraju Mohanty,  Elias Kougianos
University of North Texas, Denton

3:10PM
5A.6
An Efficient Semi-Analytical Current Source Model for FinFET Devices in Near/Sub-Threshold Regime Considering Multiple Input Switching and Stack Effect
Tiansong Cui,  Shuang Chen,  Yanzhi Wang,  Shahin Nazarian,  Massoud Pedram
University of Southern California

Chair: Srivatsa Vasudevan, Synopsys
Co-Chair: Abhilash Goyal, Oracle

1:30PM
5B.1
Assertion-Based Verification for System-Level Designs
Hassan Sohofi and Zainalabedin Navabi
University of Tehran

1:50PM
5B.2
Coverage of Compositional Property Sets under Reactive Constraints
Binghao Bao¹,  Jörg Bormann²,  Markus Wedler¹,  Dominik Stoffel¹,  Wolfgang Kunz^1
1University of Kaiserslautern, ²

2:10PM
5B.3
Automated Methods for Eliminating X Bugs
Kai-hui Chang,  Yen-ting Liu,  Chris Browy
Avery Design Systems

2:30PM
5B.4
Specification and Formal Verification of Power Gating in Processors
Amir Masoud Gharehbaghi and Masahiro Fujita
The University of Tokyo

2:50PM
5B.5
Formal Verification of Safety of Polymorphic Heterogeneous Multi-Core Architectures
Miroslav Velev and Ping Gao
Aries Design Automation

3:10PM
5B.6
Simulation and Satisfiability Guided Counter-example Triage for RTL Design Debugging
Zissis Poulos¹,  Yu-Shen Yang²,  Andreas Veneris¹,  Bao Le^1
1University Of Toronto, ²Advanced Micro Devices, Inc

Chair: Hai Li, University of Pittsburg
Co-Chair: Duo Liu, Chongqing University

1:30PM
5C.1
FastSpot: Host-Compiled Thermal Estimation For Early Design Space Exploration
Darshan Gandhi,  Andreas Gerstlauer,  Lizy John
The University of Texas at Austin

1:50PM
5C.2
Maximizing Throughput of Power/Thermal-Constrained Processors by Balancing Power Consumption of Cores
Abhishek Sinkar,  Hao Wang,  Nam Sung Kim
University of Wisconsin-Madison

2:10PM
5C.3
Building Energy-Efficient Multi-Level Cell STT-MRAM Based Cache Through Dynamic Data-Resistance Encoding
Ping Chi¹,  Cong Xu¹,  Xiaochun Zhu²,  Yuan Xie^1
1Pennsylvania State University, ²Qualcomm Incorporated

2:30PM
5C.4
Thermal Hotspot Reduction in mm-Wave Wireless NoC Architectures
Jacob Murray,  Paul Wettin,  Ryan Kim,  Xinmin Yu,  Partha Pande,  Behrooz Shirazi,  Deukhyoun Heo
Washington State University

2:50PM
5C.5
Energy-Aware Scratch-Pad Memory Partitioning for Embedded Systems
Florin Balasa¹,  Noha Abuaesh¹,  Cristian V. Gingu²,  Ilie I. Luican³,  Doru V. Nasui^4
1American University in Cairo, ²Fermilab, ³Microsoft, Inc., ⁴American International Radio, Inc.

3:10PM
5C.6
Energy Efficient Job Scheduling in Single-ISA Heterogeneous Chip-Multiprocessors
Ying Zhang¹,  Lide Duan²,  Bin Li¹,  Lu Peng¹,  Srinivasan Sadagopan^2
1Louisiana State University, ²AMD Corporation

Chair: Charles Augstine, Intel
Co-Chair: Saibal Mukhopadhyay, Georgia Tech

3:50PM
6A.1
ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes
Carlos Tadeo Ortega Otero,  Jonathan Tse,  Robert Karmazin,  Benjamin Hill,  Rajit Manohar
Cornell University

4:10PM
6A.2
An Energy-Efficient Mobile PAM Memory Interface for Future 3D Stacked Mobile DRAMs
Majid Jalalifar and Gyung-Su Byun
West Virginia University, Morgantown, WV USA

4:30PM
6A.3
Rapid Prototype and Implementation of a High-Throughput and Flexible FFT ASIP Based on LISA 2.0
Ting Chen¹,  Xiaowei Pan²,  Hengzhu Liu¹,  Tiebin Wu^1
1school of Computer, National University of Defense Technology, ²Aachen University of Technology

4:50PM
6A.4
A Spread Spectrum Clock Generator for Higher Modulatation Rate
GAUTAM KUMAR SINGH
ON Semiconductor

5:10PM
6A.5
Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous Design
Matheus Moreira¹,  Julian Pontes²,  Ney Calazans^1
1PUCRS-FACIN, ²CEA-LETI

Chair: Rajan Beera, Pall Corporation
Co-Chair: Kamesh Gadepally, Texas Instruments

3:50PM
6B.1
Statistical Analysis of Process Variation Induced SRAM Electromigration Degradation
Zhong Guan¹,  Malgorzata Marek-Sadowska¹,  Sani Nassif^2
1ECE Department, University of California, Santa Barbara, ²Austin Research Laboratory, IBM

4:10PM
6B.2
Estimating True Worst Currents for Power Grid Electromigration Analysis
Di-an Li and Malgorzata Marek-Sadowska
UCSB

4:30PM
6B.3
An Enlarged-Partition Based Preconditioned Iterative Solver for Parallel Power Grid Simulation
Le Zhang and Vivek Sarin
Texas A&M University

4:50PM
6B.4
A 3-D Fast Transform-Based Preconditioner for Large-Scale Power Grid Analysis on Massively Parallel Architectures
Konstantis Daloukas,  Nestor Evmorfopoulos,  Panagiota Tsompanopoulou,  George Stamoulis
Department of Electrical and Computer Engineering, University of Thessaly

5:10PM
6B.5
On Pattern Generation for Maximizing IR Drop
Arunkumar Vijayakumar¹,  Vinay C Patil¹,  Girish Paladugu²,  Sandip Kundu^1
1Electrical and Computer Engineering, University of Massachusetts , Amherst , USA, ²Advanced Micro Devices , Boxborough , USA

Chair: Daniela De Venuto, Polytechnic of Bari, Italy
Co-Chair: Phil Mather, Maxim

3:50PM
6C.1
Design of a CMOS Readout Circuit for Wide-Temperature Range Capacitive MEMS Sensors
Yucai Wang and Vamsy Chodavarapu
McGill University

4:10PM
6C.2
Topology Optimization of a Passive Thermal Actuator
Harald Steiner¹,  Wilfried Hortschitz¹,  Franz Keplinger²,  Thilo Sauter^1
1Center for Integrated Sensorsystems, Danube University Krems, ²Institute of Sensor and Actuator Systems, Vienna University of Technology

4:30PM
6C.3
Thermal Flow Sensors based on Printed Circuit Board Technology
Thilo Sauter,  Thomas Glatzl,  Franz Kohl,  Harald Steiner,  Almir Talic
Danube University Krems

4:50PM
6C.4
Realization of Efficient RF Energy Harvesting Circuits Employing Different Matching Techniques
Sachin Agrawal,  Sunil Kumar Pandey,  Jawar Singh,  Manoj Singh Parihar
PDPM IIITDM Jabalpur

5:10PM
6C.5
An Integrated Precision Clock Generator for Implanted Electronics with Superior Long-term Stability
Jiyuan Luan and Michael DiVita
Texas Instrument