We present the architecture of and measured results for ULSNAP: a fully-implemented ultra-low power event-driven microcontroller targeted at the bursty workloads of the sensor network application space. ULSNAP is event-driven at both the microarchitectural and circuit levels in order to minimize static power, energy per operation, and wake up energy while maximizing performance. Our 90nm test chip offers 93 MIPS at 1.2 V and 47 MIPS at 0.95 V, consuming 47pJ and 29pJ per operation respectively. Compared to state-of-the-art processors in its class, ULSNAP is on the Pareto-optimal front of the energy-performance space.