Soft errors caused by particle strikes are expected to increase as technology scales down. This is partially because more single-event transients (SET) are latched by memory elements at the primary output of combinational circuits. To speed up the assessment of SET-induced soft errors, we propose a systematic analysis method to examine the probability of SET eventually being latched. In previous work, the latching probability of SET is only modeled as a function of SET pulse width and clock period. As soft error rate also strongly depends on other timing parameters, our novel analytical model additionally includes logic gate delays and setup/hold time of memory elements. In this work, a set of closed-form expressions for the latching probability are provided for various logic gate delays and SET pulse widths. Simulation results show that the soft error rate predicted by our model matches to that obtained from random simulations. The proposed systematic analyses method achieves up to 97% average accuracy, without using extensive Monte-Carlo simulations.