In this paper, a variation-aware system-level design methodology is presented to analyze the throughput distribution under power, area and yield constraints at the early design stage of a multi-core processor. Based on compact system-level models and circuit-level Monte Carlo HSPICE simulations, the throughput distribution of a single core processor is obtained from an efficient top-down design approach that enables exploring a large multi-parameter design space spanning device-, circuit-, and system-level parameters. To reduce the impact of variations on a multi-core processor, disabling the slowest core and per-core clocking techniques are implemented and evaluated. Finally, a novel power reallocating technique that assigns more power to more power-efficient cores is proposed to further improve the yield and aggregate throughput of a multi-core processor