As the process variation is dominating to cause the clock timing variation among chips to be much large, it is widely accepted that post-silicon tunable (PST) clock buffers can effectively resolve the the clock timing violation. Since PST buffers, which can reset the clock delay to flip-flops after the chip is manufactured, imposes a non-trivial implementation area and control circuitry, it is very important to minimally allocate PST buffers while satisfying the chip yield constraint. In this work, contrary to the previous PST buffer allocation algorithms, in which the chip yield computation is performed by the (very slow) Monte-Carlo simulation, obliged to have a limited design space exploration of PST allocation, we (1) develop a graph-based chip yield computation technique which can update yields very efficiently and accurately for incremental PST buffer allocation, based on which we (2) propose a systematic (bottom-up and topdown with refinement) PST buffer allocation algorithm that is able to fully explore the design space of PST buffer allocation. Experimental results through benchmark designs show that our proposed PST buffer allocation with fast chip yield computation uses 28.5% ~ 90.1% less number of PST buffers than that by the previous works while achieving four orders of magnitude run time improvement with less than 3% ~ 5% of yield accuracy error.