ISQED 2007 CONFERENCE AT A GLANCE

Date

Time

TUTORIALS

Emerging Circuits, Power and Variability tolerant designs

Advanced Topics in DFM, DFT and SOC

Room: Monterey/Carmel

Monday 3/26/07

9:00am-5:00pm

6:30pm-8:30pm

Evening Panel Discussion EP1 & Dinner (Room: Donner)

DFM: EDA’s salvation or its excuse for being out of touch with engineering?

Tuesday 3/27/07

8:30am-10:15am

PLENARY SESSION 1P (Room: Donner)

Keynote Speeches by:

Sanjiv Taneja (Cadence), Jeong-Taek Kong (Samsung)

10:15am-10:30am

Morning Break

10:30am-12:00pm

Session 1A

Design for Manufacturing

Room: San Jose

Session 1B

Device and Circuit Reliability

Room: Santa Clara

Session 1C

Power and Thermal Management

Room: Carmel

Session 1D

Analog and Mixed Signal Design

Room: Monterey

12:00pm-1:30pm

ISQED LUNCHEON (Room: Donner/Siskiyou)

Committee Recognition Awards

Best Paper Awards

EDA to the Rescue of Silicon Roadmap

 Thomas W. Williams (Synopsys)

1:30pm-3:30pm

Session 2A
Quality and Reliability

Room: San Jose

Session 2B
Advances in Timing and Power in Physical Design

Room: Santa Clara

Session 2C
Power-aware System Design Methodologies

Room: Monterey

SESSION 2D

POSTER

EXHIBITS

Embedded Panels & Tutorials

3:30pm-3:45pm

Afternoon Break

3:45pm-5:45pm

Session 3A
Electrical Quality

Room: San Jose

Session 3B
Analog and RF Testing

Room: Santa Clara

Session 3C
Low Power Circuits

Room: Monterey

Wednesday 3/28/07

8:30am-10:15am

PLENARY SESSION 2P (Rom: Donner)

Keynote Speeches by:

Marc Duranton (NXP Semiconductors), Marc Derbey (iRoC Technologies), Joe Sawicki (Mentor Graphics)

10:15am-10:30am

Morning Break

10:30am-12:00pm

Session 4A

Package Circuit Co-design

Room: San Jose

Session 4B

High level optimization

Room: Santa Clara

Session 4C

Interconnects and Power Grids

Room: Monterey

Session 4D

Parametric Variations in Design

Room: Carmel

12:00pm-1:30pm

Lunch and Panel Discussion LP2 (Room: Donner/Siskiyou)

Do Digital Design and Variability Mix Like Oil and Water?

1:30pm-3:30pm

Session 5A

DFM Statistics

Room: San Jose

Session 5B

Timing Test and Reliability

Room: Santa Clara

Session 5C

Variation Analysis and Design

Room: Monterey

Session 5D

Lithography and OPC

Room: Carmel

3:30pm-3:45pm

 Afternoon Break

3:45pm-5:45pm

Session 6A

DFM Process

Room: San Jose

Session 6B

PDM Physical Planning

Room: Santa Clara

Session 6C

Reliability and Interconnect at the System Level

Room: Monterey

Session 6D

Design and Modeling for Soft Error Reliability

Room: Carmel