Chair: Kevin Brelsford, Synopsys
Co-Chair: Praveen Elakkumanan, IBM

10:30AM
1A.1
Variation  (Invited Paper)
Duane Boning, et al
Microsystems Technology Laboratories, MIT

11:00AM
1A.2
An MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation
Takashi Sato,  Takumi Uezono,  Shiho Hagiwara,  Kenichi Okada,  Shuhei Amakawa,  Noriaki Nakayama,  Kazuya Masu
Tokyo Institute of Technology

11:20AM
1A.3
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Rajani Kuchipudi and Hamid Mahmoodi
San Francisco State University

11:40AM
1A.4
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs
Rouwaida Kanj,  Rajiv Joshi,  Jayakumaran Sivagnaname,  JB Kuang,  Dhruva Acharayya,  Tuyet Nguyen,  Chandler McDowell,  Sani Nassif
IBM Research

Chair: Samar Saha, Synopsys
Co-Chair: Nikos Konofaos, University of the Aegean, Greece

10:30AM
1B.1
A New Simulation Method for NBTI Analysis in SPICE Environment
Rakesh Vattikonda¹,  Yansheng Luo²,  Alex Gyure²,  Xiaoning Qi²,  Sam Lo²,  Mahmoud Shahram²,  Yu Cao¹,  Kishore Singhal²,  Dino Toffolon^2
1Arizona State University, ²Synopsys Inc.

11:00AM
1B.2
Combating NBTI Degradation via Gate Sizing
Xiangning Yang and Kewal Saluja
Department of Electrical and Computer Engineering, University of Wisconsin-Madison

11:20AM
1B.3
Analytical modeling of hot-carrier induced degradation of MOS transistors for analog design for reliability
Benoit Dubois,  Jean-Baptiste Kammerer,  Luc Hébrard,  Francis Braun
Institut d'Electronique du Solide et des Systèmes

11:40AM
1B.4
A New Organic Thin-Film Transistor based Current-driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays
Aram Shin,  Sang Jun Hwang,  Seung Woo Yu,  Man Young Sung
Dept. of Electrical Engineering, Korea University

Chair: Dinesh Somasekhar, Intel
Co-Chair: Praveen Bhojwani, Texas A&M

10:30AM
1C.1
Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers
Mosin Mondal¹,  Andrew Ricketts²,  Sami Kirolos¹,  Tamer Ragheb¹,  Greg Link²,  Vijaykrishnan Narayanan²,  Yehia Massoud^1
1Rice University, ²Penn State University

11:00AM
1C.2
Dual-VDD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew
Sherif Tawfik and Volkan Kursun
University of Wisconsin – Madison

11:20AM
1C.3
Speculative Energy Scheduling for LDPC Decoding
Weihuang Wang and Gwan Choi
Texas A&M University

11:40AM
1C.4
Dynamic Power Management by Combination of Dual Static Supply Voltages
Kanak Agarwal and Kevin Nowka
IBM Corp

Chair: George Alexiou, University of Patras
Co-Chair: Haibo Wang, Southern Illinois University Carbondale

10:30AM
1D.1
Low Voltage Buffered Bandgap Reference
Peter Hazucha¹,  Fabrice Paillet¹,  Sung Moon¹,  David Rennie²,  Gerhard Schrom¹,  Donald Gardner¹,  Kenneth Ikeda¹,  Gell Gellman¹,  Tanay Karnik^1
1Intel Corporation, ²University of Waterloo

11:00AM
1D.2
A DLL Based Multiphase Hysteretic DC-DC Converter
Pengfei Li and Rizwan Bashirullah
University of Florida

11:20AM
1D.3
Statistical Timing Analysis Considering Spatial Correlations
Hong Li¹,  Cheng-Kok Koh¹,  Venkataramanan Balakrishnan¹,  Yiran Chen^2
1Purdue University, ²Synopsys

11:40AM
1D.4
Systematic Design of a Flash ADC for UWB Applications
Liang Rong,  E. Martin I. Gustafsson,  Ana Rusu,  Mohammed Ismail
Royal Institute of Technology, Sweden

Chair: Paul Tong, Pericom.
Co-Chair: Bao Liu, UCSD

1:30PM
2A.1
Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions
Arthur Nieuwoudt and Yehia Massoud
Rice University

2:00PM
2A.2
FinFET Based SRAM Design for Low Standby Power Applications
Tamer Cakici,  Keejong Kim,  Kaushik Roy
Purdue University

2:30PM
2A.3
Compact Modeling of a PD SOI MESFET for Wide Temperature Designs
Asha Balijepalli,  Joseph Ervin,  Yu Cao,  Trevor Thornton
Arizona State University

2:50PM
2A.4
Modeling of PMOS NBTI Effect Considering Temperature Variation
Hong Luo¹,  Yu Wang¹,  Ku He¹,  Rong Luo¹,  Huazhong Yang¹,  Yuan Xie^2
1Tsinghua University, ²Pennsylvania State University

3:10PM
2A.5
Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI
Jie Deng¹,  Keunwoo Kim²,  Ching-Te Chuang²,  H.-S Philip Wong^1
1Stanford University, ²IBM T. J. Watson Research Center

Chair: Martin Wang, UIUC
Co-Chair: Shahin Nazarian, University of Southern California

1:30PM
2B.1
A Low-Power Multi-Pin Maze Routing Methodology
Ahmed Youssef,  Tor Myklebust,  Mohab Anis,  Mohamed Elmasry
University of Waterloo

2:00PM
2B.2
An Aggregation-based Algebraic Multigrid Method for Power Grid Analysis
Yu-Min Lee,  Huan-Yu Chou,  Pei-Yu Huang
National Chiao-Tung University, Taiwan

2:30PM
2B.3
Design and Analysis of "Tree + Local Meshes" Clock Architecture
Gustavo Wilke and Rajeev Murgai
Fujitsu Laboratories of America, Inc.

2:50PM
2B.4
A Linear Time Algorithm For RLC Buffer Insertion
Zhanyuan Jiang,  Shiyan Hu,  Jiang Hu,  Weiping Shi
Texas A&M University

3:10PM
2B.5
Fast Crosstalk Repair by Quick Timing Change Estimation
Nahmsuk Oh,  Peivand Tehrani,  Alireza Kasnavi
Synopsys Inc.

Chair: Lech Jozwiak, Eindhoven University of Technology
Co-Chair: Tohru Ishihara, Kyushu University

1:30PM
2C.1
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
Minh Do,  Mindaugas Drazdziulis,  Per Larsson-Edefors,  Lars Bengtsson
Dept of Camputer Science & Engineering, Chalmers University of Technology

2:00PM
2C.2
Cross Layer Error Exploitation for Aggressive Voltage Scaling
Amin Khajeh Djahromi¹,  Ahmed Eltawil¹,  Fadi Kurdahi¹,  Rouwaida Kanj^2
1University of California, Irvine, ²IBM Austin Research Labs

2:30PM
2C.3
A Unified Framework for System-level Design: Modeling and Performance Optimization of Scalable Networking Systems
Hwisung Jung and Massoud Pedram
Univ. of Southern California

2:50PM
2C.4
Thermal vs Energy Optimization for DVFS-enabled Processors in Embedded Systems
Yongpan Liu¹,  Huazhong Yang¹,  Robert Dick²,  Hui Wang¹,  Li Shang^3
1Tsinghua University, ²Northwestern University, ³Queen's University

3:10PM
2C.5
A Unified Optimal Voltage Selection Methodology for Low-power Systems
Foad Dabiri,  Roozbeh Jafari,  Majid Sarrafzadeh
UCLA

Chair: Tom Jackson, Cadence Design
Co-Chair: Antonio Nunez, University of Las Palmas

3:45PM
3A.1
A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances
Andrew B. Kahng* and Rasit O. Topaloglu**
*University of California San Diego, **Advanced Micro Devices

4:15PM
3A.2
SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design
Jeong-Yeol Kim,  Ho-Soon Shin,  Jong-Bae Lee,  Moon-Hyun Yoo,  Jeong-Taek Kong
Samsung Electronics, Co., Ltd.

4:45PM
3A.3
Pareto-Front Computation and Automatic Sizing of CPPLLs
Jun Zou,  Daniel Mueller,  Helmut Graeb,  Ulf Schlichtmann
Institute for Electronic Design Automaton, Techn. Univ. Muenchen

5:05PM
3A.4
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization
Kai-hui Chang,  David Papa,  Igor Markov,  Valeria Bertacco
University of Michigan at Ann Arbor

Chair: Spyros Tragoudas, Southern Illinois University
Co-Chair: Li-C Wang, University of California, Santa Barbara

3:45PM
3B.1
Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model
Joonsung Park,  Hongjoong Shin,  Jacob A. Abraham
The University of Texas at Austin

4:15PM
3B.2
Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications
Amit Laknaur,  Rui Xiao,  Sai Raghuram Durbha,  Haibo Wang
Southern Illinois University, Carbondale

4:45PM
3B.3
High-Frequency-Measurement-Based Frequency-Variant Transmission Line Characterization and Circuit Modeling for Accurate Signal Integrity Verification
Hyunsik Kim and Yungseon Eo
Hanyang University

5:05PM
3B.4
Achieving Low-Cost Linearity Test and Diagnosis of Sigma-Delta ADCs via Frequency-Domain Nonlinear Analysis and Macromodeling
Guo Yu,  Peng Li,  Wei Dong
Texas A&M University

5:25PM
3B.5
Fully digital optimized testing and calibration technique for Sigma Delta ADC’s
Daniela De Venuto¹ and Leonardo Reyneri^2
1Politecnico di Bari, Italy, ²Politecnico di Torino, Italy

Chair: Mark Budnik, Valparaiso University
Co-Chair: Praveen Elakkumanan, IBM Semiconductor R & D Center

3:45PM
3C.1
Cell-Based Semicustom Design of Zigzag Power Gating Circuits
Youngsoo Shin and Hyung-Ock Kim
Korea Advanced Institute of Science and Technology

4:15PM
3C.2
Lookup Table-Based Adaptive Body Biasing of Multiple Macros
Byunghee Choi and Youngsoo Shin
KAIST

4:45PM
3C.3
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
Toshinori Sato¹ and Yuji Kunitake^2
1Kyushu University, ²Kyushu Institute of Technology

5:05PM
3C.4
A High Performance, Scalable Multiplexed Keeper Technique
Jaydeep Kulkarni and Kaushik Roy
Purdue University

5:25PM
3C.5
On-Line Adjustable Buffering for Runtime Power Reduction
Andrew Kahng¹,  Sherief Reda²,  Puneet Sharma^1
1University of California, San Diego, ²Brown University

Chair: Kris Verma, Silicon Valley Technical Institute
Co-Chair: Lalitha Immaneni, Intel

10:30AM
4A.1
3DFFT: Thermal Analysis of Non-Homogeneous IC using 3D FFT Green Function Method
Dongkeun Oh,  Yu Hen Hu,  Charlie Chung-Ping Chen
University of Wisconsin

11:00AM
4A.2
Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design
Eun-Seok Song,  Heeseok Lee,  Jungtae Lee,  Woojin Jin,  Kiwon Choi,  Sa-Yoon Kang
Samsung Electronics

11:20AM
4A.3
Inter-strata Connection Characteristics and Signal Transmission in Three-dimensional (3D) Integration Technology
Syed Alam,  Robert Jones,  Shahid Rauf,  Ritwik Chatterjee
Freescale Semiconductor

11:40AM
4A.4
A Design Methodology for Matching Improvement in Bandgap References
Juan Pablo Martinez Brito,  Hamilton Klimach,  Sergio Bampi
Federal University of Rio Grande do Sul

Chair: Anand Iyer, Cadence Design
Co-Chair: Masahiro Fujita, University of Tokyo

10:30AM
4B.1
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
David Zaretsky¹,  Gaurav Mittal¹,  Robert Dick²,  Prith Banerjee^1
1University of Illinois at Chicago, ²Northwestern University

11:00AM
4B.2
Efficient Transition-Mode Boolean Characteristic Function with its Application to Maximum Instantaneous Current Analysis
Cheng-Tao Hsieh,  Jian-Cheng Lin,  Shih-Chieh Chang
Dept. of Computer Science, National Tsing Hua University

11:20AM
4B.3
Transistor-Level Synthesis for Low-Power Applications
Dimitri Kagaris and Themistoklis Haniotakis
Southern Illinois University Carbondale

11:40AM
4B.4
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis
Marc Boule,  Jean-Samuel Chenard,  Zeljko Zilic
McGill University

Chair: Murat Becer, CLK Design Automation
Co-Chair: Jeffrey Fan, West Virginia University Institute of Technology

10:30AM
4C.1
Self-timed Regenerators for High-speed and Low-power Interconnect
Jae-sun Seo,  Prashant Singh,  Dennis Sylvester,  David Blaauw
Univ. of Michigan, Ann Arbor

11:00AM
4C.2
Efficient Analysis of Large-Scale Power Grids based on a Compact Cholesky Factorization
Hong Li,  Jitesh Jain,  Venkataramanan Balakrishnan,  Cheng-Kok Koh
Purdue University

11:20AM
4C.3
General Block Structure-Preserving Reduced Order Modeling of Interconnect Circuits
Ning Mi,  Sheldon Tan,  Boyuan Yan
UCR

11:40AM
4C.4
Investigating Crosstalk in Sub-Threshold Circuits
Mini Nanua¹ and David Blaauw^2
1Sun Microsystems Inc., ²University of Michigan

Chair: David Pan, University of Texas
Co-Chair: Kiran Puttaswamy, Georgia Tech

10:30AM
4D.1
A model for timing errors in processors with parameter variation
Smruti Sarangi,  Brian Greskamp,  Josep Torrellas
Univ. of IL. at Urbana Champaign

11:00AM
4D.2
Parameter-Variation-Aware Analysis for Noise Robustness
Mosin Mondal,  Kartik Mohanram,  Yehia Massoud
Rice University

11:20AM
4D.3
Future Prediction of Self-heating in Short Intra-block Wires
Kenichi Shinkai,  Masanori Hashimoto,  Takao Onoye
Osaka Univ.

11:40AM
4D.4
Thermal-Aware Placement for FPGAs using Electrostatic Charge Model
Javid Jaffari and Mohab Anis
University of Waterloo

Chair: Jay Sivagnaname, IBM
Co-Chair: Scott Hector, Freescale Semiconductor

1:30PM
5A.1
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization
Ayhan Mutlu¹,  Jiayong Le¹,  Mustafa Celik¹,  Dar-sun Tsien²,  Garry Shyu²,  Long-Ching Yeh^2
1Extreme DA Corp., ²UMC

2:00PM
5A.2
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis
Amith Singhee and Rob Rutenbar
Carnegie Mellon University

2:30PM
5A.3
Defect or Variation? Characterizing Standard Cell Behavior at 90nm and Below
Robert Aitken
ARM

2:50PM
5A.4
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology
Choongyeun Cho¹,  Daeik Kim¹,  Jonghae Kim¹,  Jean-Olivier Plouchart¹,  Daihyun Lim²,  Sangyeun Cho³,  Robert Trzcinski^1
1IBM, ²MIT, ³University of Pittsburgh

3:10PM
5A.5
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy
Uthman Alsaiari and Resve Saleh
University of British Columbia

Chair: Sreejit Chakravarty, LSI Logic
Co-Chair: George Alexiou, University of Patras

1:30PM
5B.1
Small-Delay Defect Detection in the Presence of Process Variations
Rajeshwary Tayade¹,  Savithri Sundareswaran²,  Jacob Abraham^1
1University of Texas at Austin, ²Freescale Semiconductor

2:00PM
5B.2
Function-Based Test Generation for (Non-Robust)Path Delay Faults using the Launch-Off-Capture Scan Architecture
Rajsekhar Adapa¹,  Edward Flanigan¹,  Spyros Tragoudas¹,  Michael Laisne²,  Hailong Cui²,  Tsvetomir Petrov^2
1Southern Illinois University, ²Qualcomm Incorporated

2:30PM
5B.3
On Accelerating Soft-Error Detection by Targeted Pattern Generation
Kunal Ganeshpure,  Alodeep Sanyal,  Sandip Kundu
University of Massachusetts

2:50PM
5B.4
Enhanced Identification of Strong Robustly Testable Paths
Edward Flanigan and Spyros Tragoudas
Southern Illinois University Carbondale

Chair: Sarvesh H Bharadwaj
Co-Chair: Tom Jackson, Cadence Design

1:30PM
5C.1
Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction
Zhuo Feng,  Guo Yu,  Peng Li
Texas A&M University

2:00PM
5C.2
Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance
Ning Lu and Judy McCullen
IBM

2:30PM
5C.3
Soft Clock Skew Scheduling for System-Level Variation Tolerance in Digital Signal Processing Circuits
Yang Liu¹,  Tong Zhang¹,  Jiang Hu^2
1ECSE Department, Rensselaer Polytechnic Institute, ²Department of ECE, Texas A&M University

2:50PM
5C.4
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration
Sivasubramaniam Krishnamurthy,  Somnath Paul,  Swarup Bhunia
Case Western Reserve University

3:10PM
5C.5
Designing and Validating Process-Variation-Aware Cell Libraries
Ali Dasdan¹,  Jinfeng Liu²,  Sridhar Tirumala²,  Kayhan Kucukcakar^2
1Yahoo, Inc., ²Synopsys, Inc.

Chair: Charlie Zhang, Synopsys
Co-Chair: Sheldon Tan, University of California, Riverside

1:30PM
5D.1
Transferring Optical Proximity Correction (OPC) effect into Optical Mode
Jianliang Li,  Qiliang Yan,  Lawrence Melvin III
Synopsys Inc.

2:00PM
5D.2
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts
Tetsuya Iizuka,  Makoto Ikeda,  Kunihiro Asada
University of Tokyo, JAPAN

2:30PM
5D.3
An Automated and Fast OPC Algorithm for OPC-aware Layout Design
Ye Chen,  Zheng Shi,  Xiaolang Yan
Institute of VLSI Design, Zhejiang University

2:50PM
5D.4
A New Method of Implementing Hierarchical OPC
Yufu Zhang and Zheng Shi
Zhejiang University

Chair: Larry Melvin, Synopsys
Co-Chair: Valeriy Sukharev, Ponte

3:45PM
6A.1
A New Flexible Algorithm for Random Yield Improvement
Subarna Sinha¹,  Qing Su¹,  Linni Wen¹,  Charles Chiang¹,  Frank Lee¹,  Yi-Kan Cheng²,  Jin-Lien Lin²,  Yu-Chyi Harn^2
1Synopsys, ²TSMC

4:15PM
6A.2
Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations
Arthur Nieuwoudt,  Tamer Ragheb,  Hamid Najati,  Yehia Massoud
Rice University

4:45PM
6A.3
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm
S Ramsundar¹,  Ahmad Al-Yamani²,  Dhiraj Pradhan^3
1IIT, Guwahati, ²KFUPM, ³University of Bristol

5:05PM
6A.4
Process Variation Tolerant Standard Cell Library Development using Reduced Dimension Statistical Modeling and Optimization Techniques
Shubhankar Basu,  Priyanka Thakore,  Ranga Vemuri
University of Cincinnati

5:25PM
6A.5
Redundant Via Insertion in Restricted Topology Layouts
Kevin McCullen
IBM

Chair: Rajeev Murgai, Fujitsu Laboratories of America
Co-Chair: Weiping Shi, Texas A & M University

3:45PM
6B.1
Recursive Function Smoothing of Half­-Perimeter Wirelength for Analytical Placement
Chen Li¹ and Cheng-Kok Koh^2
1Magma Design Automation, ²ECE, Purdue University

4:15PM
6B.2
Congestion Driven Buffer Planning For X-Architecture
Hongjie Bai,  Sheqin Dong,  Xianlong Hong
Tsinghua University

4:45PM
6B.3
Probabilistic Congestion Prediction with Partial Blockages
Zhuo Li¹,  Chuck Alpert¹,  Steve Quay²,  Sachin Sapatnekar³,  Weiping Shi^4
1IBM Austin Research Lab, ²IBM EDA, ³University of Minnesota, ⁴Texas A&M University

5:05PM
6B.4
OPC-Friendly Bus Driven Floorplanning
Hua Xiang¹,  Liang Deng²,  Li-Da Huang³,  Martin D.F. Wong^2
1IBM T.J. Watson Research Center, ²UIUC, ³Magma

5:25PM
6B.5
Power-Gating Aware Floorplanning
Hailin Jiang and Malgorzata Marek-Sadowska
UCSB

Chair: Ahmed Eltawil, University of California - Irvine
Co-Chair: Artur Chojnacki, PDF Solutions

3:45PM
6C.1
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs
Frederic Worm,  Patrick Thiran,  Paolo Ienne
Swiss Federal Institute of Technology Lausanne (EPFL)

4:15PM
6C.2
An Infrastructure IP for online testing of network-on-chip based SoCs
Praveen Bhojwani and Rabi Mahapatra
Texas A&M University

4:45PM
6C.3
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Mosin Mondal¹,  Tamer Ragheb¹,  Xiang Wu²,  Adnan Aziz³,  Yehia Massoud^1
1Rice University, ²AMD, ³University of Texas

5:05PM
6C.4
Virtual Channels Planning for Networks-on-Chip
Ting-Chun Huang,  Umit Yusuf Ogras,  Radu Marculescu
Carnegie Mellon University

5:25PM
6C.5
A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits
Vyas Krishnan and Srinivas Katkoori
University of South Florida

Chair: Keith Bowman, Intel
Co-Chair: Hamid Mahmoodi, San Francisco State University

3:45PM
6D.1
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
Natasa Miskov-Zivanov and Diana Marculescu
Carnegie Mellon University

4:15PM
6D.2
An SEU-Tolerant Programmable Frequency Divider
Liang Wang,  Suge Yue,  Yuanfu Zhao,  Long Fan
Beijing Microelectronics Technology Institute

4:45PM
6D.3
A TMR Scheme for SEU Mitigation in Scan Flip-Flops
Roystein Oliveira¹,  Aditya Jagirdar¹,  Tapan Chakraborty^2
1Rutgers University, ²Alcatel.Lucent

5:05PM
6D.4
Variation Impact on SER of Combinational Circuits
Ramakrishnan Krishnan,  Rajaraman Ramanarayanan,  Suresh Srinivasan,  Vijaykrishnan Narayanan,  Yuan Xie,  Mary Jane Irwin
Penn State University

5:25PM
6D.5
MEMESTAR: A Simulation Framework for Reliability Evaluation over Multiple Environments
Christian Hescott,  Drew Ness,  David Lilja
University of Minnesota

Chair: Syed M. Alam, Freescale Semiconductor
Co-Chair: Zhen Guo, Conexant Systems

2D.1
Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and non-Inverting Repeaters Insertion
Charbel Akl and Magdy Bayoumi
University of Louisiana at Lafayette

2D.2
A 8b 10Ms/s Low Power Pipelined A/D Converter
Bi Yuan,  Yi Zhang,  Lili He
San Jose State University

2D.3
First-order Continuous-time Sigma-delta Modulator
Yamei Li and Lili He
San Jose State University

2D.4
Reducing EPL Alignment Errors for Large VLSI Layouts
Yokesh Kumar and Prosenjit Gupta
International Inst. of Information Tech., Hyderabad, India

2D.5
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS
Zhiyu Liu and Volkan Kursun
UW-Madison

2D.6
Efficient Signal Integrity Verification of Multi-Coupled Transmission Lines with Asynchronously Switching Non-Linear Drivers
Taeyong Je and Yungseon Eo
Hanyang University

2D.7
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals
Ling Zhang¹,  Hongyu Chen²,  Bo Yao³,  Kevin Hamilton⁴,  Chung-Kuan Cheng^1
1UCSD, ²Synopsys Inc., ³Mentor Graphics Inc., ⁴Qualcomm Inc.

2D.8
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
Bao Liu
UC San Diego

2D.9
Tests on Symmetry and Continuity between BSIM4 and BSIM5
Xudong Niu
Peking University

2D.10
Interface Specification Assurance Methods
Naiyong Jin
East China Normal University

2D.11
Multi-Dimensional Circuit and Micro-Architecture Level Optimization
Zhenyu (Jerry) Qi¹,  Matthew Ziegler²,  Stephen V. Kosonocky²,  Jan M. Rabaey³,  Mircea R. Stan^1
1University of Virginia, ²IBM T. J. Watson Research Center, ³University of California at Berkeley

2D.12
A Test-Structure To Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays
Nigel Drego,  Anantha Chandrakasan,  Duane Boning
MIT

2D.13
Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits
Rishi Bhooshan
Texas Instruments India Ltd

2D.14
Processing High Volume Scan Test Results for Yield Learning
Phil Burlison¹,  Dennis Ciplickas²,  Alfred Crouch^1
1Inovys Corporation, ²PDF Solutions, Inc.

2D.15
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-architecture
Shen Weixiang¹,  Cai Yici¹,  Hong Xianlong¹,  Hu Jiang²,  Lu Bing^3
1Tsinghua University, ²Texas A&M University, ³Cadence Design

2D.16
Comparative Robustness of CML Phase Detectors for Clock And Data Recovery Circuits
David Rennie and Manoj Sachdev
University of Waterloo

2D.17
Inductive Fault Analysis approach for test and diagnosis of DNA sensor arrays
Daniela De Venuto
Politecnico di Bari

2D.18
Fine-Grained Redundancy in Adders
Patrick Ndai¹,  Shih-Lien Lu²,  Dinesh Somasekhar^2
1Purdue University, ²Intel Corporation

2D.19
MEMS Failure Probability Prediction and Quality Enhancement Using Neural Networks
Abby Ilumoka¹ and Honglang Tan^2
1University of Hartford, ²

2D.20
Variation Aware Timing based Placement using Fuzzy Programming
Mahalingam Venkataraman and Nagarajan Ranganathan
University of South Florida

2D.21
Variation Analysis of CAM Cells
Amol Mupid¹,  Madhu Mutyam²,  N. Vijaykrishnan¹,  Y. Xie¹,  M. J. Irwin^1
1The Pennsylvania State University, ²International Institute of Information Technology

2D.22
Design-for-Manufacture for Multi Gate Oxide CMOS Process
Qi Lin,  Mei Ma,  Tony Vo,  Jenny Fan,  Xin Wu,  Richard Li,  Xiao-Yu Li
Xilinx, Inc.

2D.23
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure
Yu-Min Kuo¹,  Cheng-Hung Lin¹,  Chun-Yao Wang¹,  Shih-Chieh Chang¹,  Pei-Hsin Ho^2
1NTHU, Taiwan, ²Synopsys, USA

2D.24
Power Delivery Aware Floorplanning for Voltage Island Designs
Yici Cai,  Bin Liu,  Jin Shi,  Qiang Zhou,  Xianlong Hong
Tsinghua University

2D.25
Passive Modeling of Interconnects By Waveform Shaping
Boyuan Yan¹,  Pu Liu¹,  Sheldon X.-D. Tan¹,  Bruce McGaughy^2
1University of California, Riverside, ²Cadence Design Systems Inc.

2D.26
A Power Network Synthesis Method for Industrial Power Gating Designs
Kaijian Shi,  Zhian Lin,  Yi-Min Jiang
Synopsys

2D.27
Reducing the Energy Consumption in Fault-tolerant Distributed Embedded Systems with Time-Constraint
Yuan Cai¹,  Sudhakar M. Reddy¹,  Bashir M. Al-Hashimi^2
1University of Iowa, ²University of Southampton

2D.28
Challenges in Evaluations for a Typical-Case Design Methodology
Yuji Kunitake¹,  Akihiro Chiyonobu¹,  Koichiro Tanaka¹,  Toshinori Sato^2
1Kyushu Institute of Technology, ²Kyushu University

2D.29
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-based FPGAs
Hamid Zarandi¹,  Seyed Ghassem Miremadi²,  Dhiraj K. Pradhan¹,  Jimson Mathew^1
1University of Bristol, ²Shrif University of Technology

2D.30
Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors
Xiaofang Wang¹ and Sotirios Ziavras^2
1Villanova University, ²New Jersey Institute of Technology

2D.31
A High frequency PWM controller in HV Bi-CMOS process considering SOI self-heating
Santosh K Panigrahi and Gautam K Singh
Pulsecore Semiconductor (India) Pvt. Ltd.

2D.32
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Joon-Sung Yang¹,  Anand Rajaram²,  Ningyu Shi¹,  Jian Chen¹,  David Z. Pan^1
1University of Texas at Austin, ²University of Texas at Austin/Texas Instruments

2D.33
Built-In Test of RF Mixers Using RF Amplitude Detectors
Chaoming Zhang,  Ranjit Gharpurey,  Jacob Abraham
CERC, Univeristy of Texas at Austin

2D.34
Glitch Control with Dynamic Receiver Threshold Adjustment
Michael Skoufis,  Haibo Wang,  Themistoklis Haniotakis,  Spyros Tragoudas
Southern Illinois University

2D.35
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O
Yong Sin Kim and Sung-Mo Kang
UCSC

2D.36
A Fault Tolerant Design Methodology for Threshold Logic Gates and its Optimizations
Manoj Kumar Goparaju and Spyros Tragoudas
Southern Illinois University

2D.37
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization
Kumar Yelamarthi and Henry Chen
WSU

2D.38
Wavelet­-Based Passivity Preserving Model Order Reduction with Adaptive Frequency Selection
Mehboob Alam,  Arthur Nieuwoudt,  Yehia Massoud
Rice University

2D.39
System Level Estimation of Interconnect Length in the Presence of IP Blocks
Taraneh Taghavi,  Ani Nahapetian,  Majid Sarrafzadeh
University of California, Los Angeles (UCLA)

2D.40
Energy-Minimization Model for Fill Synthesis
Rasit Topaloglu
Advanced Micro Devices

2D.41
On-chip Inductance in X Architecture Enabled Designs
Santosh Shah,  Arani Sinha,  Li Song,  Narain D. Arora
Cadence Design Systems

2D.42
Impact of Variability on Clock Skew in H-tree Clock Networks
Ashok Narasimhan and Ramalingam Sridhar
University at Buffalo (SUNY)