International Symposium on Quality Electronic Design (ISQED)
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ISQED 2012 Conference At-a-Glance

Monday, March 19, 2012

9:00am–5:00pm

ISQED 2012 Tutorials

Best Practices and Opportunities with Emerging Technologies

Room: Sunnyvale

 

Upholding Moore’s Law by Transistor Innovations

Design-assisted Semiconductor Manufacturing

3D Integration with Interposer and TSVs: Requirements for technology infrastructure

Interface Architectures for Low Power and High Performance Memory

Challenges and Opportunities of 3-D IC System Architecture and Design

3D IC Test Challenges and Emerging Solutions

12 Noon–12:50pm

Lunch Tutorial (Sponsored By Mentor Graphics)

Room: Sunnyvale

Why Your Extraction Tool Needs to Be Like a Speed Skater at 28nm!

Tuesday, March 20, 2012

8:15am–10:00am

Plenary Session 1P

Room: Silicon Valley

Keynote Speeches:

Taming the Challenges in Advanced Node Design

Tom Beckley, Senior Vice President, Research and Development, Custom IC and Signoff, Silicon Realization Group, Cadence Design Systems, Inc.

 

Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap

Luigi Capodieci, Director DFM/CAD - R&D Fellow – GLOBALFOUNDRIES

 

Resistive switching concepts: towards a paradigm change in using non-volatile memories?

Christophe Muller, Professor, Aix-Marseille University

10:00am-10:20am

Morning Break

Exhibits

10:00am –7:00pm

Atrium

 

10:20am–12 Noon

Session 1A

Test and Measurement

Room: Sunnyvale

Session 1B

Reliable System Design

Room: Morgan Hill

Session 1C

System Frameworks and Tools

Room: Freemont

Session 1D

Semiconductor Failure Modes and Mitigation for Critical Systems

Room: Santa Clara

12 Noon–1:30am

ISQED Luncheon

Room: Silicon Valley

ISQED Quality Award (IQ Award 2012)

ISQED Quality Quest Award (Q2 Award 2012)

Best Paper Awards

Committee Recognition Awards

 

Luncheon Speech

Applications Driven Analog Technology Development and Innovation

Venu Menon, Vice President, Analog Technology Development, Technology and Manufacturing Group,

Texas Instruments

1:30pm–3:30pm

Session 2A

Thermal and Power in 3D ICs

Room: Sunnyvale

Session 2B

Low Power Communication Circuits

Room: Morgan Hill

Session 2C

Process-Induced Variability & Hot Spot Detection

Room: Freemont

Session 2D

Power -Aware Testing and Test Strategies for Low Power Devices

Room: Santa Clara

3:30pm–3:50pm

Afternoon Break

3:50pm–5:30pm

Session 3A

Emerging Topics in EDA

Room: Sunnyvale

Session 3B

Design & Analysis of Emerging Devices

Room: Morgan Hill

Session 3C

Variation-Aware Design Methodologies

Room: Freemont

Session 3D

Embedded systems’ Virtualization: Concepts, Issues and Challenges

Room: Santa Clara

5:30pm–7:00pm

Poster Papers & Mixer

Room: Atrium

Wednesday, March 21, 2012

8:15am–10:00am

Plenary Session 2P

Room: Silicon Valley

Keynote Speeches:

Tech and Space: A Symbiotic Relationship

Rich Goldman, VP Corporate Marketing & Strategic Alliances, Synopsys

 

The End of Performance Scaling?

Dean M. Tullsen, Professor, University of California, San Diego

 

10x Power Reduction with 10x More Variability: Does it Make Sense?

Jos Huisken, Principal Researcher, IMEC-NL

10:00am–10:20am

Morning Break

10:20am–12 Noon

Session 4A

Physical Design

Room: Sunnyvale

Session 4B

Robust SRAM Design

Room: Morgan Hill

Session 4C

3D Effects on Package Co-Design

Room: Freemont

12 Noon–1:30pm

Lunch Break

1:30pm–3:30pm

Session 5A

Advanced Analysis & Characterization for Sub-Micron Design

Room: Sunnyvale

Session 5B

Power-Aware Design

Room: Morgan Hill

Session 5C

Circuit-Level Variability & Manufacturability

Room: Freemont

3:30pm–3:50pm

Afternoon Break

3:50pm–5:30pm

Session 6A

Verification & Silicon Debug

Room: Sunnyvale

Session 6B

Challenges & Opprotunities in New Technologies

Room: Morgan Hill

Session 6C

Energy-Aware System Design

Room: Freemont

 

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