Chair & Moderator: Anand Iyer, Advanced Micro Devices
Tuesday, March 20, 2012
Hans Manhaeve and Esko Mikkola, Ridgetop Group, Inc.
The mounting issues of decreased yield and reliability from nanoscale IC processes require advanced approaches to the measurement and mitigation of device degradation and variance. Shrinking process geometries, with their corresponding reduction in device lifetimes, have broad implications to critical applications having long intended design lifetimes and are a major concern to the long term reliability of safety-critical systems in aerospace and automotive applications. Common semiconductor failure modes include among others Time Dependent Dielectric Breakdown (TDDB), hot carrier damage (HCI), Negative Bias Temperature Instability (NBTI). Die-level prognostic test structures can detect and help mitigate the untimely failures in critical systems. These test structures, with variance measurement capabilities, also provide an effective platform for improved process-aware design for improved yields. This tutorial addresses concepts of in-situ test structures as a solution to product yield enhancement, process reliability qualification and reliability monitoring throughout the lifetime of the product and include practical application examples.
Hans Manhaeve received the Electrical Engineering Degree (MSc) in Electronics from KIHWV (Technical University of Oostende) in 1987. After performing his military duties, he joined the KIHWV, now KHBO, as a staff member of the microelectronics department (associated lab of IMEC), where he lectured ASIC-design, testability and design for test, IC testing, the use of CAD-tools and informatics. He conducted stimulated and coordinated research in the areas of integrated circuit design, test of integrated circuits and design for test. In co-operating with industrial partners he developed current measurement solutions and related test strategies. He was involved in several EU Research and education projects as well as in national funded projects. He coordinated the Copernicus project UBISTA, focusing on current based (self-) test strategies for analogue and mixed signal circuits. While working at KHBO he received the Ph.D. Degree in Electronic Engineering, from the University of Hull (UK) in February 1997, after successfully defending a thesis on methods to enhance IC testability and the application of IDDQ testing. In 1999, he joined IMEC as a researcher and at the end of 1999 he took the initiative to set up the KHBO/IMEC spin-off company Q-Star Test recently renamed to Ridgetop Europe, focusing on marketing supply current test solutions. He’s currently CEO of Ridgetop Europe, guest professor at KHBO and serves as reviewer for the EC. He is IEEE member, is involved in various well recognized international workshops and conferences, is an active member of the IEEE-CS ETTTC (European group of the Test Technology Technical Committee) as well as of the TTTC. He delivered active contributions to several national and international conferences and workshops. He authored/co-authored more than 80 papers of which more than 45 papers on current measurement modules and current-based test strategies and holds several patents on IDDQ / IDDT measurement solutions and related test techniques, strategies and methods.
Esko Mikkola - Originally from Finland, Dr. Mikkola earned his doctoral degree from the University of Arizona (UA), Electrical and Computer Engineering (ECE), in August 2008. After graduating, he joined Ridgetop Group where he now serves as a principal engineer. During his doctoral studies, Dr. Mikkola developed behavioral modeling methodologies for ADCs with special attention to accuracy and reliability concerns for modern deep submicron ICs. Dr. Mikkola’s VHDL-AMS-based hierarchical simulation method for data converter aging simulations proved up to 3,000 times faster than Cadence® Virtuoso® Spectre® Circuit Simulator – while accuracy stayed within reasonable limits. The developed simulation code included physics-based TID models. Dr. Mikkola has also published a novel single event transient (SET) mitigation strategy for high-speed voltage comparators used in ADCs. During his three years at Ridgetop Dr. Mikkola has served as a principal investigator in many SBIR programs, including a phase 2 program with NASA to develop a radiation hard ADC for a digital beam forming radar. He also designed a calibration circuitry for a 16-bit commercial ADC and sub circuits for a radiation hardened ADC for the super Large Hadron Collider (s-LHC) at CERN, Switzerland. He also developed an innovative architecture for a self-calibrated high-speed time-interleaved ADC and has become an expert on reliability issues of electronics on-board space missions. Dr. Mikkola’s ProChekTM reliability and radiation effect qualification tool design won a phase II award from US Air Force with excellent performance reviews for the phase I period. Before joining full time Mikkola worked as an intern at Ridgetop as a mixed-signal design engineer and developed a built-in self-test (BIST) circuit for space radiation effects on ADCs and in-situ reliability monitor ICs for degradation effects in CMOS systems
Tuesday, March 20, 2012
Patrick Girard and Nicola Nicolici, LIRMM/CNRS, McMaster University
Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This tutorial provides knowledge in this area. It is organized into three main parts. The first one gives necessary background and discusses issues arising from excessive power dissipation during test application. The second part provides comprehensive knowledge of structural and algorithmic solutions that can be used to alleviate such problems. The last part surveys low power design techniques and shows how these low power devices can be tested safely without affecting yield and reliability. EDA solutions for considering power during test and design-for-test are also discussed in the last part of the tutorial.
Patrick GIRARD received a M.S. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research Director at CNRS (French National Center for Scientific Research), and Head of the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier - France). His research interests include all aspects of digital testing and memory testing, with emphasis on critical constraints such as timing and power. From 2006 to 2010, Patrick Girard was Vice-Chair of the European Test Technology Technical Council (ETTTC) of the IEEE Computer Society. He has served on numerous conference committees including ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design Automation and Test in Europe (DATE), IEEE International Test Conference (ITC), IEEE International Conference on Computer Design (ICCD), IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE Asian Test Symposium (ATS), and ACM/IEEE International Symposium on Low Power Electronic Design (ISLPED). Patrick Girard is the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE). He is an Associate Editor of the IEEE Transactions on VLSI Systems and the Journal of Electronic Testing – Theory and Applications (JETTA - Springer). From 2005 to 2009, he was an Associate Editor of the IEEE Transactions on Computers. He is a co-editor of the book “Power-Aware Testing and Test Strategies for Low Power Devices”, Springer, 2009, and a co-author of the book “Advanced Test Methods for SRAMs – Effective Solutions for Dynamic Fault Detection in Nanoscale Technologies”, Springer, 2009. Patrick Girard has been involved in several European research projects (ESPRIT III ATSEC, EUREKA MEDEA, MEDEA+ ASSOCIATE, IST MARLOW, MEDEA+ NanoTEST, CATRENE TOETS) and has managed industrial research contracts with major companies like Infineon Technologies, Intel, Atmel, ST-Ericsson, STMicroelectronics, etc. He has supervised 26 PhD dissertations and has published 6 books or book chapters, 36 journal papers, and more than 150 conference and symposium papers on these fields. Patrick Girard is a Golden Core Member of the IEEE Computer Society.
Nicola NICOLICI is an Associate Professor in the Department of Electrical and Computer Engineering at McMaster University, Canada. He received the Dipl. Ing. degree in Computer Engineering from the “Politehnica” University of Timisoara, Romania (1997), and a Ph.D. in Electronics and Computer Science from the University of Southampton, U.K. (2000). His research interests are in the area of computer-aided design and test. He has authored over fifty research papers and one book in this area and received the IEEE TTTC Beausang Award for the Best Student Paper at the International Test Conference (ITC 2000) and the Best Paper Award at the IEEE/ACM Design Automation and Test in Europe Conference (DATE 2004). Currently he is on the technical program committee for the DATE, IEEE/ACM Design Automation Conference (DAC), IEEE European Test Symposium (ETS), IEEE Defect and Fault Tolerance Symposium (DFT), IEEE Asian Test Symposium (ATS), IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE Workshop on Silicon Debug and Diagnosis (SDD), and he serves as the Program Co-Chair for Diagnostic Services in Network-on-Chips Workshop. He was the guest co-editor for a special issue on Silicon Debug and Diagnosis (to be published by IET Proceedings on Computers and Digital Techniques) and a special issue on Low Power Test (to be published by for the Journal of Electronic Testing – Theory and Applications). He is a member of the ACM SIGDA and the IEEE Computer and Circuits and Systems Societies.
Tuesday, March 20, 2012
Fabiano Hessel and Alexandra Aguiar, Faculty of Informatics, PUCRS, Brazil
The talk will begin with an overview of trends in embedded system virtualization including its current use and impact on embedded software design quality. Then, a review of some virtualization use cases in general purpose computing and its similarities and differences from embedded systems use. Next, hardware and software techniques that allow virtualization in embedded systems’ context are presented along with current implementation use cases. Design challenges and trends for embedded virtualization are shown as the talk is concluded by discussing how virtualization can enable new and innovative devices
Fabiano Passuelo Hessel is a Professor of Computer Science at Pontifical Catholic University of Rio Grande do Sul (PUCRS), Brazil. He received his Ph.D. in Computer Science from Universite Joseph-Fourier, TIMA laboratory France. He is the head of Embedded System Group. He was the Associate Editor of the ACM Transaction on Embedded Computer Systems - Special Issue on Rapid System Prototyping, General Chair and Program Chair of RSP (2007, 2008, 2011). He had several publications in prestigious conferences and journals, book chapters and books. His research interests are embedded real-time systems, real time operating systems and MPSoC systems.
Alexandra Aguiar is a Ph.D. student at Pontifical Catholic University of Rio Grande do Sul (PUCRS), Brazil. The Computer Science Master's degree was received from PUCRS University. She is an assistant professor of Computer Science at Centro Universitario La Salle (UNILASALLE), Brazil. Since March of 2009 she is one of the leaders of Hellfire Project in the Embedded Systems Group and her research interests are embedded real-time system, real-time operating systems, MPSoC systems and embedded systems virtualization.