For any question please contact the publication committee by sending email to firstname.lastname@example.org. Note the following important dates:
IMPORTANT DATES (Midnight, US Pacific Time)
| FINAL Paper Submission Deadline
||Oct. 11, 2016|
|Acceptance Notification||Dec. 5, 2016|
|Camera-Ready Paper Due||January 9, 2017|
A pioneer and leading multidisciplinary conference, ISQED accepts and promotes papers related to the manufacturing, design and EDA. Authors are invited to submit papers in the various disciplines of high level design, circuit design (digital, analog, mixed-signal, RF), test & verification, design automation tools; processes; flows, device modeling, semiconductor technology, advance packaging, and biomedical & bioelectronic devices. All past Conference proceedings & Papers have been published in IEEE Xplore digital library and indexed by Scopus.
The details of various topics of paper submission are as follows:
Hardware accelerators for machine learning (ML) and deep learning algorithms including Support Vector Machines, Neural Networks, Hidden Markov Model Decoding, and Genetic Algorithms. ML algorithms optimized for CPUs or general purpose GPUs (GPGPUs). FPGA-accelerated implementations of ML algorithms. Hardware implementations of ML algorithms for applications like image/object recognition, computer vision, speech recognition, and natural language processing. ML-based intelligence in IoT under highly constrained energy/power requirements. System-wide partitioning for deep learning algorithms: algorithm training and recognition from cloud/server to IoT node.
Hardware security attacks including (but not limited to) side-channel attacks, reverse engineering, tampering, and Trojans. Supply-chain integrity. Security for memory technologies. Hardware-based security primitives including PUFs, TRNGs, and ciphers. Design of encryption circuits. Security, privacy, trust protocols, and trusted information flow using hardware security primitives. Trusted design automation using untrusted tools. Trusted manufacturing including split manufacturing, remote IC enabling/disabling, watermarking, and fingerprinting. Techniques and metrics for hardware/software usage metering; evaluating system-data/hardware-design confidentiality, integrity, and authenticity; and, ensuring system security.
Optimization-based methodologies that address the interaction between design (custom, semi-custom, ASIC, FPGA, RF, memory, etc.) and advanced-node manufacturing techniques such as multiple patterning, EUV lithography, DSA lithography, and advanced interconnect (e.g., air gap for local interconnect, Si photonics, etc.). Modeling, analysis, and optimization of technology implications on performance metrics like power consumption, timing, area, and cost. Design methods and tools to improve yield and manufacturability.
Hardware and software formal-, assertion-, and simulation-based design verification techniques to ensure the functional correctness of hardware early in the design cycle. DFT and BIST for digital designs, analog/mixed-signal IC's, SoC's, and memories. Test synthesis and synthesis for testability. DFT economics, DFT case studies. DFT and ATE. Fault diagnosis, IDDQ test, novel test methods, effectiveness of test methods, fault models and ATPG, and DPPM prediction. SoC/IP testing strategies. Design methodologies dealing with the link between testability and manufacturing.
EDA and physical design tools, processes, methodologies, and flows that address issues such as: large-scale SoC design, low-power design, noise sensitivity reduction, reliable clock distribution, timing closure, parasitic extraction, and reliable power grid design and analysis. Design tools for analysis/ tolerance of variation, aging, and soft-errors. Design and maintenance of hard and soft IP blocks, including methods and tools for analysis, comparison, and qualification of IP blocks. Challenges and solutions of integrating, testing, qualifying and manufacturing IP blocks from multiple vendors. Application of EDA to non-traditional problems such as smart power grid, solar energy, etc.
Emerging processes and device technologies and implications on IC design. Emerging technologies including tunnel FETs, steep switching slope devices, horizontal/vertical nanowires, carbon nanotubes, and other nano-devices. Device design and circuit optimization in emerging non-volatile memory and logic, such as STT-RAM, PC-RAM, R-RAM, and Memristors. Use of emerging devices for cognitive, neuromorphic, or quantum computing. Specialty technologies such as MEMs, CIS co-integration with application processors for the IoT market.
Low power, high-performance, and robust design of logic, memory, analog, RF, programmable logic, and FPGA circuits. Techniques for leakage control, power optimization, and power management including integrated voltage regulators. Clock-generation and distribution circuits, including all-digital PLLs and DLLs. Low power on-chip and chip-to-chip interconnect solutions. ADC's and DAC's . Adaptive digital circuits and systems. Soft-error and fault-tolerant circuits. Circuit design for reliability effects such as gate oxide integrity, electromigration, ESD, HCI, NBTI, PBTI etc. On-chip process, voltage, temperature, and aging sensors and monitoring.
Hardware design for IoT including digital logic, memory design, wireless communications, sensor design & integration, energy harvesting, signal processing, and power management. Sensor and actuator devices for use in IoT applications like Smart Home/Office automation, robotics, connected vehicles, aircraft, wearable systems, implantable electronics, environmental monitoring, and other industrial uses. Device technologies for sensors including MEMS, magnetic, optical, chemical, and biological. Software design for smart sensors including data processing algorithms and information fusion. Sensor network design and processing. Cyber-Physical Systems – Design, Methodologies & Tools.
Emerging system-level design paradigms, methods and tools aiming at quality of systems including multi-core processors, graphics processors, embedded systems, SoC, novel accelerator designs, and heterogeneous architecture designs. System-level trade-off analysis and multi-objective (e.g. yield, power, delay, area, etc.) optimization. System level power and thermal management. The influence of nanometer technology issues on the system level design. System level modeling and simulation to characterize effects of process, voltage, temperature, and aging on power, performance, and reliability.
Innovative packaging technologies including 3D IC, 2.5D or interposer, and multi-chip module and their impact on system design. Design techniques, methodologies, flows and EDA solutions for vertically integrated circuits/chips such as 2.5D, TSV-based 3D, and monolithic 3D design including novel partitioning, power delivery design, clock tree design, reliable high-frequency signal communication, thermal design & heatsink/cooling methods, and design-for- yield techniques. Modeling and mitigation of via-to-via and via-to-device interactions for 3D ICs. Design of die-to-die interfaces in 3D/2.5D ICs. Design-for-testability for 3D/2.5D ICs. System-level design issues in 3D/2.5D. Die-package co-design.
Paper submission must be done on-line through the conference web site: www.isqed.org. The guidelines for the final paper format are provided on the conference web site. Authors should submit original, unpublished papers along with an abstract of about 200 words. The manuscripts should not exceed SIX (6) pages, should not use smaller than 10pt font size, and must be consistent with the format provided in the conference website: www.isqed. org. The manuscripts longer than 6 pages and/or written in less than 10-pt font sizes will not be reviewed. To permit a blind review, do not include name(s) or affiliation(s) of the author(s) on the manuscript and abstract. The complete contact author information needs to be entered separately.
The manuscripts identifying the name and/or affiliations of the authors in the submitted manuscript will be rejected without review. Please check the as-printed appearance of your paper before sending your paper. In case of any problems email email@example.com.
See the MS Word template at the bottom of this page. Use the on-line paper submission procedure by clicking the following link: ON-LINE. If you have problem accessing the paper submission site it is located at:https://www.softconf.com/g/isqed2017
Selected papers from ISQED 2017 will be invited for submission to two (2) journal special issues:
IET Cyber-Physical Systems: Theory & Applications
Integration, the VLSI Journal
The selection process for these special issues will take place after the conference is completed and will be based on reviewer feedback and the quality of the conference presentation.
Several workshop/tutorial sessions will be held on the first day, and would offer valuable opportunities for practicing professionals to refresh or upgrade their skills in quality-based IC design techniques, methodologies and tools. These sessions are intended to supplement the conference by providing in depth, practical and proven design solutions. Workshops/Tutorials will be taught by experts in the field, who are intimately involved with the issues and solutions in their perspective areas, from both industry and academia. If interested in offering a tutorial, please send your tutorial proposals to the ISQED workshop/tutorial committee to firstname.lastname@example.org
The proposal should include:
You may send your proposal by email as text or as an Adobe PDF file. The presentations must be technical, up to date, relevant, and target the design community. Marketing presentations will not be accepted. In order to meet the conference timeline, we would like to have your proposal no later than Nov. 25, 2016. Please check the archive section of the web site for a listing of past tutorials.