International Symposium on Quality Electronic Design (ISQED)
CFP
Submit Paper

Program at a Glance

Register
Sponsor/Exhibit

Press Room
Press Room

Skyscraper Advert Placeholder

ISQED 2011 Conference At-a-Glance

Monday, March 14, 2011

9:00am–5:00pm

ISQED 2011 Tutorials

***Holistic Approach to Low Power Design: Best Practices and Opportunities with Emerging Technologies***

SRAM and Logic Circuit Techniques for Low Power Design in 32nm and Below

Automated Design and Porting of Analog/Mixed-signal Circuits

Current and Electric Field Induced Switching of Ferromagnets for Low-power Memory Applications

Application of Spintronics for MRAM and Memristor-based Computing

Hybrid Electrical Energy Storage Systems

System Level Power Management for Cellular Chipsets

Room: Bayshore

 
12 Noon–12:50pm

Lunch

Tuesday, March 15, 2011

8:15am–10:00am

Plenary Session 1P

Sponsored by Cadence Design Systems

Room: Winchester/Stevens Creek

Keynote Speeches:

Design for manufacturing (DFM) Innovations and advances for IC Design  

Vinod Kariat - Cadence Design Systems

*****

Multitechnology Hyperintegration Platform: the technology crystal ball 

Kamran Eshraghian -Innovation Labs

*****

For how much longer can Moore's Law hold?  

R.Fabian W.Pease -Stanford University

10:00am-10:20am

Morning Break

Exhibits

10:00am –7:00pm

Mezzanine East/West

 

10:20am–12 Noon

Session 1A

Device Aging: Analysis and Design

Room: Lafayette

Session 1B

Analog and 3D ICs

Room: San Tomas

Session 1C

Low Power Circuits, Sensors, and Memory

Room: Lawrence

Session 1D

Modeling, Abstraction, and Verification of Industrial Flash Memories

Room: Bayshore

12 Noon–1:30am

ISQED Luncheon

Sponsored by Synopsys

 

Room: Winchester/Stevens Creek

ISQED Quality Award (IQ Award 2011)

ISQED Quality Quest Award (Q2 Award 2011)

Best Paper Awards

Committee Recognition Awards

____________________________________________

Keynote

Eshel Haritan - Synopsys

Virtual Prototyping for HW-SW co-verification and co-debugging in a

multi processor, complex chip designs

1:30pm–3:30pm

Session 2A

Lithography and 3D Integration

Room: Lafayette

Session 2B

New Ideas in Digital Design Automation

Room: San Tomas

Session 2C

System frameworks and tools

Room: Lawrence

Session 2D

Stress Management for 3D ICs using Through-Silicon-Vias

Room: Bayshore

3:30pm–3:50pm

Afternoon Break

3:50pm–5:30pm

Session 3A

Variation and Noise Aware Design

Room: Lafayette

Session 3B

Physical Design Issues in Custom Circuits and FPGAs

Room: San Tomas

Session 3C

Verification Validation and Test

Room: Lawrence

Session 3D

Verification of Power Managed Wireless SoCs

Room: Bayshore

5:30pm–7:00pm

Poster Papers & Mixer

Room: Mezzanine

Wednesday, March 16, 2011

8:15am–10:00am

Plenary Session 2P

Sponsored by Mentor Graphics

Room: Winchester/Stevens Creek

Keynote Speeches:

Ensuring Known Good IP for Successful IC Development  

Juan C. Rey - Mentor Graphics

*****

The State of 3D Circuit Integration and Its Effect on Design  

Robert Patti - Tezzaron Semiconductor

*****

Enabling the Smart-Connected Home  

Manas Saksena - Marvell Semiconductors

 

10:00am–10:20am

Morning Break

10:20am–12 Noon

Session 4A

Variation, Reliability, and Test

Room: Lafayette

Session 4B

Package co design for reliability and signal/Power Integrity

Room: San Tomas

Session 4C

System Design Considerations

Room: Lawrence

Electronic Design Education Conference

Session I

Room: Bayshore

12 Noon–1:30pm

Lunch Tutorial

Sponsored by Mentor Graphics

Signoff-driven Custom Physical Design 

Room: Winchester/Stevens Creek

1:30pm–3:30pm

Session 5A

Error Resilient Design

Room: Lafayette

Session 5B

Routing, Signal Integrity, and Timing Closure

Room: San Tomas

Session 5C

Power Delivery and Estimation

Room: Lawrence

Electronic Design Education Conference

Session II

Room: Bayshore

3:30pm–3:50pm

Afternoon Break

3:50pm–5:30pm

Session 6A

Design Methodologies for CMOS and Beyond

Room: Lafayette

Session 6B

Advanced Devices and Manufacturing Technologies

Room: San Tomas

Session 6C

New Ideas in Analog Design Automation

Room: Lawrence

Electronic Design Education Conference

Session III

Room: Bayshore

 

Thursday, March 17, 2011

Affiliated Event: Design for Reliability Workshop – Stress Management for 3D ICs Using Through Silicon Vias


ISQED