Monday, March 14, 2011
Chair & Moderator: Rajiv Joshi, IBM T J Watson Research Center, Syed M. Alam, Everspin Technologies, Inc.
Muhammad M. Khellah
A range of circuit-level techniques focusing on low-power design of both SRAM and logic circuits will be presented. A key enabler to power reduction is dropping the minimum supply voltage (or Vmin). With feature size scaling and associated increase in intrinsic device variability, it is becoming ever harder to meet aggressive Vmin targets without excessive area penalty. PVT adaptive “assist schemes” to improve Vmin of 6T and 8T SRAM cells will be presented as a means for low-power and low-area SRAM array design. Furthermore, the need to margin for the worst-case dynamic voltage, temperature, and aging conditions increases Vmin. Recent schemes targeting reducing Vmin guard-band through timing error resiliency will be discussed in this regards. Finally, we will also touch upon recent issues in fine grain power gating (sleep) as well as on-die power delivery schemes for total power reduction at the block level.
Magma Design Automation
Methods to automate the design of analog circuits using equation-based optimization have begun to gain traction. Hierarchical analog circuits with thousands of design variables are now being efficiently optimized using these techniques, including circuits such as ADCs, PLLs, SERDES components, and a host of standard analog circuits such as opamps and bandgaps (collectively referred to as flexible analog IP cells, or 'Flex-cells'). Using these equation-based methods, circuits the size of a PLL can be designed in a matter of hours over multiple PVT corners, which allows for both fast, automated process porting and an effective way to explore the system-level trade-offs of an analog design. In this tutorial, we intend to show the process needed to capture the equations for a common analog Flex-cell, a Low Drop-Out Voltage Regulator, and give the audience a sense of both the steps involved and a larger sense of where these techniques are most valuable.
University of California, Berkeley
We shall present recent results on modeling of spin transfer torque devices. Our model combines a full quantum transport simulation with the magnetization dynamics. Our modeling shows excellent agreement with experiments and allows for predictive modeling for circuit and system level analysis. In the second portion of the talk, we shall discuss the possibility of switching a magnet just by applying an electric field without any driving current.
Hai (Helen) Li
Polytechnic Institute of New York University
This tutorial will give a broad view on application of Spintronics for magnetic RAM (MRAM) and memristor-based computing. We will start with the fundamental of Spintronic devices, and then extend to spin torque transfer RAM (STT-RAM) and Spintronic memristors. Their application in computing systems will be discussed in detail. The design challenges, such as the impact of process variations, will be addressed and the implications to design will be discussed.
Naehyuck Chang1, Massoud Pedram2
1Seoul National University, 2University of Southern California
As of today, no single type of electrical energy storage (EES) element fulfills high energy density, high power delivery capacity, low cost per unit of storage, long cycle life, low leakage, and so on, at the same time. Following a review of conventional EES, we introduce a HEES (hybrid EES) system comprising heterogeneous EES elements based on the concepts of computer memory hierarchy. We introduce HEES design considerations aiming at the optimal charge management for various cost metrics.
System level power management requires a holistic approach that encompasses disciplines ranging from process technology, hardware design, software, modeling, and architecture. Power is one metric that must be balanced with cost, resource, and schedule constraints. This presentation will describe the scope of system level power management to enable a viable, marketable product.