techcomlist

Following is the preliminary list of committee members. All members are encouraged to contact the technical programs chair, as soon as possible to confirm their active participation in the committee.

ISQED 2009 Technical Program Committee (TPC)

EDA Methodologies, Tools, Flows & IP Cores; Interoperability and Reuse (EDA)

James Lei - Altera (Chair)

Antonio Nunez - University of Las Palmas GC, Spain (Co Chair)

Committee Members:

Anand Iyer - Achronix

Magdy Abadir - Freescale Semiconductor

Min Zhao - Freescale Semiconductor

Sudeep Pasricha - Colorado State University

Masahiro Fujita - University of Tokyo

Vassilios Gerousis – Cadence

Oliver Sentieys – IRISA, University of Rennes

He Jin - Peking University

Andre Reis - Nangate

Eui-Young Chung - Yonsei University

Reviewer(s):

Shubhankar Basu - Cadence Design Systems

Xiaolong Yuan - University of California, Riverside

Carlos Valderrama, Mons Politechnic, Belgium

EDA tools addressing design for manufacturing, yield, and reliability. Management of design process, design flows and design databases. EDA tools interoperability issues and implications. Effect of emerging technologies, processes & devices on design flows, tools, and tool interoperability. Emerging EDA standards. EDA design methodologies and tools that address issues which impact the quality of the realization of designs into physical integrated circuits. IP modeling and abstraction. Design and maintenance of technology independent hard and soft IP blocks. Methods and tools for analysis, comparison and qualification of libraries and hard IP blocks. Challenges and solutions of the integration, testing, qualifying, and manufacturing of IP blocks from multiple vendors. Third party testing of IP blocks. Risk management of IP reuse. IP authoring tools and methodologies.

Design for Manufacturability/Yield & Quality (DFMQ)

Peter Wright - Synopsys (Chair)

Peter O’Shea - PMC-Sierra (Co-Chair)

Commitee Members:

Gareth Keane - PMC-Sierra Inc.

Hidetoshi Matsuoka - Fujitsu Limited

Kevin Brelsford – Synopsys

Jayakumaran Sivagnaname – IBM

Praveen Elakkumanan – IBM

Puneet Gupta – UCLA

Rajendran Panda - Freescale Semiconductor

Vladamir Zolotov – IBM

Saumil Shah - Magma Design Automation

Jianliang Li - Synopsys

Azadeh Davoodi - University of Wisconsin Madison

Jeffrey Fan - Florida International University*

Saraju P. Mohanty, Univ of North Texas

Valeriy Sukharev - Mentor Graphics

Reviewer(s):

Yiming Li - National Chiao Tung University

Mahalingam Venkataraman - University of Southern Florida

DFM/DFY/DFQ definitions, methodologies, matrices, and standards. Quality-based design methodologies and flows for custom, semi-custom, ASIC, FPGA, RF, memory, networking circuit, etc. Design flows and methodologies for SoC, and SiP. Analysis, modeling, and abstraction of manufacturing process parameters and effects for highly predictable silicon performance. Design and synthesis of ICs considering factors such as: signal integrity, transmission line effects, OPC, phase shifting, and sub-wavelength lithography, manufacturing yield and technology capability. Design for diagnosability, defect detection and tolerance; self-diagnosis, calibration and repair. Design and manufacturabilty issues for Digital, analog, mixed signal, RF, MEMS, opto-electronic, biochemical-electronic, and nanotechnology based ICs. Redundency and other yield improving techniques. Global, social, and economic implications of design quality.

Package - Design Interactions & Co-Design (PDI)

Kamesh Gadepally - NSC (Chair)

Lalitha Immaneni - Intel (Co Chair)

Commitee Members:

Dong G. Kam - IBM T.J. Watson Research Center

Kemal Aygun - Intel

Per Viklund - Mentor Graphics

Rasit Topaloglu - AMD

Takashi Sato - Tokyo Institute of Technology

Alain Caron – IBM

Reviewer(s):

Ravi Mahajan - Intel

Concurrent circuit, package, and PCB/PWB design and effect on quality. EDA tools and methodologies dealing with the IC Packaging electrical and thermal modeling and simulation for improved quality of product. SoC versus system in a package (SiP): design and technology solutions and tradeoffs; MCM, BGA, Flip Chip, and other innovative packaging techniques for various applications such as mixed-signal and RFIC.

Design Verification and Design for Testability (DFVT)

Li-C Wang - University of Santa Barbara (Chair)

Sreejit Chakravarty - LSI Logic (Co-Chair)

Committee Members:

Daniela De Venuto - Polytechnic of Bari

Greg Billus - Texas Instruments

George Alexiou - University of Patras and RA-CTI

Haibo Wang – Souther Illinois University

Jayanta Bhadra - Freescale Semiconductor

Jennifer Dworak - Brown University

Ramyanshu Datta - Texas Instruments

Spyros Tragoudas - Southern Illinois University

Tao Feng - Cadence

Miroslav Velev - Consultant, USA

Arnaud Virazel - lirmm

Reviewer(s):

Zhen Guo - Conexant

Smita Krishnaswamy - University of Michigan

Moiz Khan - Synopsys

Hardware and Software, Formal and simulation based design verification techniques to ensure the functional correctness of hardware early in the design cycle. DFT and BIST for digital and SoC. DFT for analog/mixed-signal ICs and systems-on-chip, DFT/BIST for memories. Test synthesis and synthesis for testability. DFT economics, DFT case studies. DFT and ATE. Fault diagnosis, IDDQ test, novel test methods, effectiveness of test methods, fault models and ATPG, and DPPM prediction. SoC/IP testing strategies. Design methodologies dealing with the link between testability and manufacturing.

Power-conscious Devices, Interconnects, and Circuits (PCC)

Aswin Mehta - Texas Instruments (Chair)

Mark Michael Budnik – Valparaiso University (Co-Chair)

Committee Members:

Amir H. Ajami - Magma Design

Dinesh Somasekhar – Intel

Hirokazu Yonezawa - Matsushida Electric (Panasonic)

Murat Becer – CLK Design Automation

Naehyuck Chang - Seoul National University

Nikos Konofaos - University of Patras, Greece

Peng Li - Texas A & M University

Rajiv Joshi – IBM

Sheldon Tan - UC Riverside

Nanda Gopal - Synopsys

Reviewer(s):

Quentin Chen - Cadence

Yu Wang - University of Tsinghua, China

Yici Cai - University of Tsinghua, China

Yu-Min Lee - National Chiao Tung University

Maziar Goudarzi - Kyushu University, Japan

João M. S. Silva - INESC-ID

Device, substrate, interconnect, circuit , and IP block modeling and simulation techniques; CMOS, Bipolar, and SiGe HBTs device modeling in the context of advanced digital, RF and high-speed circuits. Modeling and simulation of novel device and interconnect concepts. Signal integrity analysis: coupling, inductive and charge sharing noise; noise avoidance techniques. Modeling statistical process variations to improve design margin and robustness, use of statistical circuit simulators. Power grid design, analysis and optimization; timing analysis and optimization; thermal analysis and design techniques for thermal management. Power-conscious design methodologies and tools; low power devices, circuits and systems; power-aware computing and communication; system-level power optimization and management. Design techniques for leakage current management. Design of robust 3D Integrated Circuits. Successful applications of TCAD to circuit design. Impacts of process technologies on circuit design and capabilities (e.g. low-Vt transistors versus increased off-state leakages) and the accuracy, use and implementation of SPICE models that faithfully reflect process technologies.

Emerging/Innovative Process & Device Technologies and Design Issues (EDT)

Paul Tong - Pericom (Chair)

Bao Liu, University of Texas - San Antonio (Co-Chair)

Committee Members:

Ali-Afzali-Kusha, University of Tehran

Jae Joon Kim, IBM

Saibal Mukhopadhyay, Georgia Institute of Technology

Syed Alam, EverSpin Technologies, Inc.

Yehia Massoud, Rice University

Volkan Kursun, Hong Kong University of Science and Technology

Renato Perez Ribas - UFRGS

Kingsuk Maitra - AMD

Yiran Chen - Seagate Technology

Deming Chen - University of Illinois, Urbana-Champaign

Sunil P Khatri - Texas A&M University

Arijit Raychowdhury - Intel

Reviewer(s):

Kiran Puttaswamy - Georgia Institute of Technology

Xiao-Dong Yang - ICScape

Raghunath Murali - Georgia Institute of Technology

Hua Fang - PDF

Emerging processes & device technologies and implications on IC design with respect to design’s time to market, yield, reliability, and quality. Emerging issues in DSM CMOS: e.g. sub-threshold leakage, gate leakage, technology road mapping and technology extrapolation techniques. New and novel technologies such as SOI, Double-Gate (DG)-MOSFET, Gate-All-Around (GAA)-MOSFET, Vertical-MOSFET, strained CMOS, high-bandwidth metallization, 3D integrated circuits, nanodevices, etc.

Design of Reliable Circuits and Systems (DFR)

Keith A Bowman - Intel (Chair)

David Pan - UT (Co-Chair)

Committee Members:

Hamid Mahmoodi – San Francisco State University

Lei Wang - University of Connecticut

Masanori Hashimoto - Osaka University

Raimund Ubar - Tallinn Technical University, Estonia

Soroush Abbaspour – IBM

Yong-Bin Kim – Northeastern University

Dongsheng Ma - University of Arizona

Srinivas Bodapati - Intel

Reviewer(s):

David Rennie - University of Waterloo

Rishi Bhooshan - Texas Instruments

Device and process reliability issues and effect on design of reliable circuits and systems. ESD design for digital, mixed signal and RF applications. Exploration of critical factors such as noise, substrate coupling, cross-talk and power supply noise. Significance and trends in process reliability effects such as gate oxide integrity, electromigration, ESD, etc., and their relation to electronic design.

System-level Design, Methodologies & Tools (SDM)

Lech Jozwiak- Eindhoven University of Technology (Chair)

Artur Chojnacki – M2000, Inc. (Co-Chair)

Committee Members:

Ahmed Eltawil – University of California, Irvine

Christophe Wolinski - University of Rennes, France

Fabiano Hessel – PUCRS

Hana Kubatova - Czech Technical University, Prague

Krzysztof Kuchcinski - Lund Institute of Technology, Sweden

Priyadarsan Patra – Intel

Roman Lysecky – University of Arizona

Sao-Jie Chen - National Taiwan University

Srinivas Katkoori - University of South Florida

Fadi Kurdahi – University of California, Irvine

Tohru Ishihara - Kyushu University, Japan

Klaus Waldschmidt - University of Frankfurt

Maziar Goudarzi - Kyushu University

Jose Silva Matos, Professor DEEC – FEUP, Porto, Portugal

Sung Woo Chung - Korea University Seoul

Reviewer(s):

Hwisung Jung - University of Southern California

Praveen S. Bhojwani - Sun Microsystems, Inc.

Emerging system-level design paradigms, methods and tools aiming at quality. ESL design process and flow management. System-level design modeling, analysis, synthesis, estimation and verification for correct high-quality hardware/software systems. Development of reliable, responsive, secure, manufacturable, and defect-tolerant systems. New concepts, methods and tools addressing the hardware and system design complexity, multitude of aspects, manufacturability, and usage of technology information and manufacturing feedback in the system-, RTL- and logic level design. The influence of the nanometer technologies’ issues on the system-, RTL- and logic-level design. System-level trade-off analysis and multi-objective (yield, power, delay, area …) optimization. Effective and efficient development, implementation, analysis and validation of large SoCs integrating IP blocks from multiple vendors. Global, social, and economical implications of Electronic System and Design Quality. Emerging standards and regulations influencing system quality.

Physical Design, Methodologies & Tools (PDM)

Rajeev Murgai - Magma Design Automation (Chair)

Martin Wong - UIUC (Co-Chair)

Committee Members:

Eli Bozorgzadeh - University of California, Irvine, USA

Hai Zhou – Northwestern University

Janet Meiling - University of Arizona

Jiang Hu - Texas A & M University

Makoto Ikeda - University of Tokyo

Wenting Hou - Synopsys

Weiping Shi – Texas A&M University

Hao Li - University of North Texas

Shiyan Hu - Michigan Technological University

Haoxing Ren, IBM T J Watson Research Center

Reviewer(s):

Jane Wang – Cadence, Taiwan

Mely Chen Chi - Chung Yuan Christian University

Hua Xiang - IBM

George Ontko - Texas Instruments

Physical design for manufacturing; Physical synthesis flows for correct-by-construction quality silicon, implementation of large SoC designs. Tool frameworks and data-models for tightly integrated incremental synthesis, placement, routing, timing analysis and verification. Placement, optimization, and routing techniques for noise sensitivity reduction and fixing. Algorithms and flows for harnessing crosstalk-delay during physical synthesis. Tool flows and techniques for antenna rule and electromigration rule avoidance and fixing. Spare-cell strategies for ECO, decoupling capacitance and antenna rule fixing. Physical planning tools for predictable power-aware circuits. Reliable clock tree generation and clock distribution methodologies for Gigahertz designs. EDA tools, design techniques, and methodologies, dealing with issues such as: timing closure, R, L, C extraction, ground/Vdd bounce, signal noise/cross-talk /substrate noise, voltage drop, power rail integrity, electromigration, hot carriers, EOS/ESD, plasma induced damage and other yield limiting effects, high frequency effects, thermal effects, power estimation, EMI/EMC, proximity correction & phase shift methods, verification (layout, circuit, function, etc.).

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International Society for Quality Electronic Design (ISQED Org.) Copyright © 1998-2009 ISQED. All rights reserved. Revised: June 18, 2009