International Symposium on Quality Electronic Design (ISQED)
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ISQED Conference At-a-Glance

Monday, March 22, 2010

9:00am–5:00pm

Tutorials

Room: Monterey/Carmel

Design Technologies and Opportunities in Nano-Scale Era:

Beyond 32 nm Technology

Energy Efficient Digital Circuit Design

Alternate Memories

SOC Verification

3-D CAD Design

Microprocessor Architecture Impacts on Power

12 Noon–12:50pm

Lunch Tutorial

New Approaches to Parasitic Extraction

Tuesday, March 23, 2010

8:30am–10:15am

Plenary Session 1P

Room: Fir/Oak

Keynote Speeches by:

Sponsored by Mentor Graphics

Ramanan Thiagarajah, Sr. Director of Product and Test Engineering, Inphi Corp

Shankar Krishnamoorthy, CTO, Mentor Graphics

Mark Gogolewski, CTO & CFO, Denali Software

10:15am-10:30am

Morning Break

10:30am–12 Noon

Session 1A

SRAM Design for Quality

Room: Monterey

Session 1B

Mixed Signal and Power Control Circuits

Room: Carmel

Session 1C

Guaranteeing Timing Performance

Room: Santa Clara

Session 1D

Analog Design For Reliability

Room: San José

12 Noon–1:30am

ISQED Luncheon

Room: Fir/Oak)

Annual ISQED Quality Award (IQ Award 2010)

Sponsored by Synopsys

Best Paper Awards

Committee Recognition Awards

Luncheon Keynote

Test of the Future: Some Thoughts for the Next Decade

Antun Domic, Senior VP & GM, Synopsys

1:30pm–3:30pm

Session 2A

Lithography & DFM

Room: Monterey

Session 2B

Power Aware Memory Design

Room: Carmel

Session 2C

Embedded Tutorial

Field solvers for advanced analog and digital designs

Room: Santa Clara

Embedded Session 2D

Poster Papers

Room: Donner

Exhibits
Open
1:30–6:30pm

3:30pm–3:45pm

Afternoon Break

 
3:45pm–5:45pm

Session 3A

Variability: Design, Test, and Characterization

Room: Monterey

Session 3B

Emerging Device and Design Techniques

Room: Carmel

Session 3C

Power & Performance Issues in System-level Design

Room: Santa Clara

Embedded Session 3D

Poster Papers

Room: Donner

 
5:45pm–6:30pm

Evening Break

 
6:30pm–8:30pm

Panel Discussion & Dinner

Room: Fir/Oak

Long Life Cycle Design - Is It Really Different from Traditional CE?

Sponsored by Mentor Graphics

Wednesday, March 24, 2010

8:30am–10:15am

Plenary Session 2P

Room: Fir/Oak

Keynote Speeches by:

Krishna Yarlagadda, President & CEO, HelloSoft

Aki Fujimura, CEO - D2S & eBeam Initiative

Steve Glaser – VP Strategy & Planning - Cadence Design Systems

10:15am–10:30am

Morning Break

10:30am–12 Noon

Session 4A

Parametric and delay test

Room: Monterey

Session 4B

Package & IC Co-Design

Room: Carmel

Session 4C

Embedded Tutorial

Field Solver Solutions for System Level & RF

Room: Santa Clara

Session 4D

Embedded Tutorial

A Scalable Methodology for Analog & Mixed-Signal Verification

Room: San José

12 Noon–1:30pm

Lunch Break

1:30pm–3:30pm

Session 5A

Advances in Power Distribution, Placement and Routing

Room: Monterey

Session 5B

Aging Analysis & Mitigation

Room: Carmel

Session 5C

Test, Quality, Cost and Debug

Room: Santa Clara

Session 5D

System-level NoC, SoC and ASIC design

Room: San José

3:30pm–3:45pm

Afternoon Break

3:45pm–5:45pm

Session 6A

Clocking Strategy for Modern Low Power Multi-Core and Structured ASICs

Room: Monterey

Session 6B

Modeling and Analysis of Temperature and Power

Room: Carmel

Session 6C

Fault Tolerant Design

Room: Santa Clara

Session 6D

Quality system level design

Room: San José


ISQED