In this paper, we present an ESD characterization and sensitivity analysis methodology using a Technology Computer-Aided Design (TCAD)-based gate-grounded NMOS (GGNMOS) digital twin. First, the virtual GGNMOS device is created by simulating the fabrication process of a 0.35μm CMOS technology. The digital twin is then calibrated to a known device by matching the transmission line pulse (TLP) IV curves. Second, a one-at-a-time (OAT) sensitivity analysis is performed for various device/process parameters. In particular, the impact of device/process parameters on the trigger point, breakdown point, and on-resistance was quantified. Statistical box plots are used to interpret the results of the sensitivity analysis. Finally, the OAT analysis is leveraged to generate a targeted labeled dataset that includes all the failure modes with respect to the ESD design window. This proposed platform opens the door to applying machine learning (ML) to the design and refinement of the ESD protection circuit/window while accounting for process variation.