This work evaluates the on-chip variability of the Anderson PUF by instantiating 128 designs on a Nexys A7 FPGA and collecting 100 UART samples per configuration using a lightweight Python automation script. MUX distance (MDIST) and flip-flop (FF) placement are varied to assess placement sensitivity, uniformity, and uniqueness. Preliminary results show wide intra-chip uniformity variation with no consistent trend; MDIST = 2 yields the most balanced outputs, while larger distances produce strong skew. These findings highlight the impact of routing and placement and provide guidance for reliable FPGA-based implementations.