In-memory computing is an emerging computing paradigm that sidesteps challenges inherent to deep learning acceleration in conventional systems. Along with the development of neuromorphic architectures, resistive random-access memory (RRAM) has paved the way for in-memory computing by processing mixed-signal operations in fully parallel fashion. In this work, we design and implement several working prototypes of in-memory operators using a custom 65nm CMOS/RRAM technology node fabricated on a 300mm wafer. Specifically, an array of hafnium-oxide RRAM cells is built in a crossbar structure to support high-throughput matrix multiplications at low energy and area consumption. Building upon these efficient RRAM, applications of pixel detection and non-stateful/stateful Boolean operations are presented. Our introduced approaches alleviate the intermediate data movement and parallelize the computations, thereby yielding orders of magnitude improvement in energy and area efficiency over the equivalent CMOS design.