In this presentation, I will review joint work with SkyWater and Intrinsix on the development of an RRAM yield test vehicle. The design integrates 8.8 Mb of RRAM together with control logic and read/write circuitry for parametric testing. All timing signals and analog bias voltages are generated on chip and are programmable via SPI, allowing the chip to interface with generic test equipment. A low-noise, offset compensated sense amplifier ensures high-fidelity readout across a conductance range from 3.3 to 425 microsiemens. Future work will look into open-sourcing this design for re-use by the community.