Abstract Many promising interconnect materials have been proposed to replace traditional Copper interconnects. In this paper, an efficient interconnect technology/memory co-design framework is developed by integrating a realistic cell library to enable a large design space exploration for various emerging interconnect technologies. To minimize the H-tree delay and energy overheads, we propose three H-tree technology options using four interconnect materials and benchmark them against their traditional Copper counterparts for optimal SRAM performance, such as the energy-delay-area product (EDAP) and energy-delay product (EDP). Various array- and interconnect-level design parameters are co-designed to quantify the graphene-based interconnects true potential for optimal performance.