A Bit-Parallel Deterministic Stochastic Multiplier

Sairam Sri Vatsavai and Ishan Thakkar
University of Kentucky


Abstract

This paper presents a novel bit-parallel deterministic stochastic multiplier, which improves the area-energy-latency product by up to 6.7x10^4, while improving the computational error by 32.2%, compared to three prior stochastic multipliers.