HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications

Divy Pandey1, Vishesh Mishra1, Saurabh Singh1, Sagar Satapathy2, Babita Jajodia1, Dip Sankar Banerjee2
1Indian Institute of Information Technology Guwahati, 2Indian Institute of Technology Jodhpur


In recent times, approximate computing is widely employed in the design of power-aware hardware architectures. Approximate computing techniques can be used to benefit a major class of error-resilient applications. It has emerged as a computing paradigm that can efficiently cater several popular applications that can tolerate bounded imprecision in results. Applications such as image processing, machine learning, and deep learning extensively use multiplication and addition operations on 8-bit numbers. This work proposes an 8-bit High-Performance Approximate Multiplier (HPAM) for error resilient applications. HPAM is capable of providing significant speedup at application end while simultaneously maintaining high accuracy standards. It is designed the motivation of providing an broad error bound thus making it worthy in catering applications with high accuracy demands as well as low accuracy standards. Additionally, an approximate version of conventional ripple carry adder (RCA), a Segmented Ripple Carry Approximate Adder (SRCA) is also proposed along with this work. To validate the efficacy of the proposed design, its performance is compared with the conventional Wallace tree multiplier and the existing state-of-the-art designs such as TOSAM, DSM, and LETAM. On average, HPAM provides a speedup of 27.08% and 48.06% more accurate results in comparison to the existing state-of-the-art designs.