Multi-Objective Variation-Aware Sizing for Analog CNFET Circuits

Zahra Heshmatpour, Lihong Zhang, Howard Heys
Memorial University of Newfoundland


Carbon nanotube field-effect transistors (CNFETs) are one of the promising candidates to substitute CMOS technology for next-generation integrated circuits. Process variation currently hinders wide adoption of CNFET technology, many techniques have been developed to overcome the fabrication variation for digital CNFET circuits while analog CNFET circuits generally lack a proper approach to avoid performance failure. In this paper, we present a multi-objective deterministic sizing flow considering carbon nanotube parameter process variation for analog CNFET sizing design. To the best of our knowledge, this is the first work that systematically studies a robust design methodology for analog CNFET circuits. To ensure the performance robustness, we use a design centering approach for circuit sizing to obtain the optimal value of design parameters against carbon nanotube process variation. We take advantage of the new normal boundary intersection (NBI) method in combination with our modified generalized boundary curve (GBC) method to develop our CNFET variation-aware multi-objective optimization. With two analog CNFET circuits tested for our optimization methodology, the experimental results demonstrate that our proposed method can reach a better estimation of the Pareto front compared to the other state-of-the-art multi-objective methods.