Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny Designs

Xiangdong Wei and Xinfei Guo
Shanghai Jiao Tong University


As powerful enablers of the agile hardware development, high level languages offer tremendous benefits of boosting the design productivity and shortening the development gap between software and hardware. While the increasing diversity of such languages also complicates the decision making processes in terms of which approach to pick as a designer. In this work, we perform a comprehensive study of two of the most popular high level design approaches (Chisel and High level synthesis) by looking into the hardware implementation details and PPA metrics. Different from other existing comparison studies, where complex algorithms were picked as benchmark designs, our study carefully selected designs that were at a relatively small scale. We have maintained exactly the same coding style and design details to decouple the impact of purposeful optimizations users might introduce in the beginning of the evaluation. Through such study, we aim to understand root causes that set the differences among designs resulted from high level approaches. We present preliminary results, detailed metric comparisons and comparison methodology in this paper.