Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs

Li-Wei Chen1, Yao-Nien Sui2, Tai-Cheng Lee2, I-Ching Tsai3, Tai-Wei Kung3, En-Cheng Liu3, Yun-Chih Chang3, Yih-Lang Li2, Mango C.-T. Chao2
1National Yng-Ming Chiao-Tung University, 2National Yang-Ming Chiao-Tung University, 3Realtek Semiconductor Corp


Timing closure is crucial to successful very large-scale integration designs. In the physical design stage, designers must iterate their design to develop a layout that can resolve timing violations, which is relatively time consuming. The challenges of pre-routing timing prediction include delay prediction for routed wires and behavior analysis for post-route timing optimization. We present a path-based, pre-routing timing prediction mechanism using a machine-learning methodology and extracted features, which are the essential properties associated with path delay and timing optimization. Experimental results demonstrated that the slack values of the timing paths predicted using the proposed model are much closer to those at the post-route stage reported by an electronic design automation (EDA) tool, with R-square scores ranging from 0.949 to 0.988. Moreover, the proposed model exhibits considerable superiority in predicting the n most-timing-critical paths compared with the EDA tool at the post–clock tree synthesis (CTS) stage. The number of timing-critical paths that were the same as the 100 most-timing-critical paths reported by an EDA tool at the post-route stage ranged from 67 to 88, whereas only 1 to 45 were reported at the post-CTS stage.